1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 *
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
8 *
9 * Some init for sunxi platform.
10 */
11
12 #include <cpu_func.h>
13 #include <init.h>
14 #include <log.h>
15 #include <mmc.h>
16 #include <i2c.h>
17 #include <serial.h>
18 #include <spl.h>
19 #include <sunxi_gpio.h>
20 #include <asm/cache.h>
21 #include <asm/gpio.h>
22 #include <asm/io.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/spl.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/timer.h>
27 #include <asm/arch/tzpc.h>
28 #include <asm/arch/mmc.h>
29
30 #include <linux/compiler.h>
31
32 struct fel_stash {
33 uint32_t sp;
34 uint32_t lr;
35 uint32_t cpsr;
36 uint32_t sctlr;
37 uint32_t vbar;
38 uint32_t sp_irq;
39 uint32_t icc_pmr;
40 uint32_t icc_igrpen1;
41 };
42
43 struct fel_stash fel_stash __section(".data");
44
45 #ifdef CONFIG_ARM64
46 #include <asm/armv8/mmu.h>
47
48 static struct mm_region sunxi_mem_map[] = {
49 {
50 /* SRAM, MMIO regions */
51 .virt = 0x0UL,
52 .phys = 0x0UL,
53 .size = 0x40000000UL,
54 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
55 PTE_BLOCK_NON_SHARE
56 }, {
57 /* RAM */
58 .virt = 0x40000000UL,
59 .phys = 0x40000000UL,
60 .size = CONFIG_SUNXI_DRAM_MAX_SIZE,
61 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
62 PTE_BLOCK_INNER_SHARE
63 }, {
64 /* List terminator */
65 0,
66 }
67 };
68 struct mm_region *mem_map = sunxi_mem_map;
69
board_get_usable_ram_top(phys_size_t total_size)70 phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
71 {
72 /* Some devices (like the EMAC) have a 32-bit DMA limit. */
73 if (gd->ram_top > (1ULL << 32))
74 return 1ULL << 32;
75
76 return gd->ram_top;
77 }
78 #endif /* CONFIG_ARM64 */
79
80 #ifdef CONFIG_XPL_BUILD
gpio_init(void)81 static int gpio_init(void)
82 {
83 __maybe_unused uint val;
84 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
85 #if defined(CONFIG_MACH_SUN4I) || \
86 defined(CONFIG_MACH_SUN7I) || \
87 defined(CONFIG_MACH_SUN8I_R40)
88 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
89 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
91 #endif
92 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || \
93 defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I_R40) || \
94 defined(CONFIG_MACH_SUN9I)
95 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
96 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
97 #else
98 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
99 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
100 #endif
101 sunxi_gpio_set_pull(SUNXI_GPF(4), SUNXI_GPIO_PULL_UP);
102 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
103 sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
104 sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
105 sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
106 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
107 defined(CONFIG_MACH_SUN7I) || \
108 defined(CONFIG_MACH_SUN8I_R40))
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
110 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
111 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
112 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
114 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
115 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
116 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
118 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
119 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
120 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
121 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
122 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
123 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
124 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
125 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
126 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
127 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
128 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
129 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
131 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
132 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
133 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
134 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
135 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
136 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616)
137 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0);
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0);
139 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
140 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_A133)
141 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_H616_GPH_UART0);
142 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN50I_H616_GPH_UART0);
143 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
144 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN55I_A523)
145 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), 2);
146 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), 2);
147 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
148 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
149 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
150 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
151 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
152 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
153 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
154 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
155 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
156 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
157 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
158 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
159 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
160 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528)
161 sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6);
162 sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6);
163 sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
164 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
165 sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
166 sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
167 sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP);
168 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
169 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
170 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
171 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
172 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3)
173 sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2);
174 sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2);
175 sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP);
176 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
177 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
178 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
179 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
180 #elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528)
181 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7);
182 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7);
183 sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP);
184 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
185 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
186 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
187 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
188 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
189 !defined(CONFIG_MACH_SUN8I_R40)
190 sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1);
191 sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1);
192 sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
193 #else
194 #error Unsupported console port number. Please fix pin mux settings in board.c
195 #endif
196
197 /*
198 * Update PIO power bias configuration by copying the hardware
199 * detected value.
200 */
201 if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
202 IS_ENABLED(CONFIG_SUN50I_GEN_NCAT2)) {
203 val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
204 /* TODO: A523: keep only the lower two bits? */
205 writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
206 }
207 if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) {
208 val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
209 writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
210 }
211
212 return 0;
213 }
214
spl_board_load_image(struct spl_image_info * spl_image,struct spl_boot_device * bootdev)215 static int spl_board_load_image(struct spl_image_info *spl_image,
216 struct spl_boot_device *bootdev)
217 {
218 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
219 return_to_fel(fel_stash.sp, fel_stash.lr);
220
221 return 0;
222 }
223 SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
224 #endif /* CONFIG_XPL_BUILD */
225
226 #define SUNXI_INVALID_BOOT_SOURCE -1
227
suniv_get_boot_source(void)228 static int suniv_get_boot_source(void)
229 {
230 /* Get the last function call from BootROM's stack. */
231 u32 brom_call = *(u32 *)(uintptr_t)(fel_stash.sp - 4);
232
233 /* translate SUNIV BootROM stack to standard SUNXI boot sources */
234 switch (brom_call) {
235 case SUNIV_BOOTED_FROM_MMC0:
236 return SUNXI_BOOTED_FROM_MMC0;
237 case SUNIV_BOOTED_FROM_SPI:
238 return SUNXI_BOOTED_FROM_SPI;
239 case SUNIV_BOOTED_FROM_MMC1:
240 return SUNXI_BOOTED_FROM_MMC2;
241 /* SPI NAND is not supported yet. */
242 case SUNIV_BOOTED_FROM_NAND:
243 return SUNXI_INVALID_BOOT_SOURCE;
244 }
245 /* If we get here something went wrong try to boot from FEL.*/
246 printf("Unknown boot source from BROM: 0x%x\n", brom_call);
247 return SUNXI_INVALID_BOOT_SOURCE;
248 }
249
sunxi_egon_valid(struct boot_file_head * egon_head)250 static int sunxi_egon_valid(struct boot_file_head *egon_head)
251 {
252 return !memcmp(egon_head->magic, BOOT0_MAGIC, 8); /* eGON.BT0 */
253 }
254
sunxi_toc0_valid(struct toc0_main_info * toc0_info)255 static int sunxi_toc0_valid(struct toc0_main_info *toc0_info)
256 {
257 return !memcmp(toc0_info->name, TOC0_MAIN_INFO_NAME, 8); /* TOC0.GLH */
258 }
259
sunxi_get_boot_source(void)260 static int sunxi_get_boot_source(void)
261 {
262 struct boot_file_head *egon_head = (void *)SPL_ADDR;
263 struct toc0_main_info *toc0_info = (void *)SPL_ADDR;
264
265 /*
266 * On the ARMv5 SoCs, the SPL header in SRAM is overwritten by the
267 * exception vectors in U-Boot proper, so we won't find any
268 * information there. Also the FEL stash is only valid in the SPL,
269 * so we can't use that either. So if this is called from U-Boot
270 * proper, just return MMC0 as a placeholder, for now.
271 */
272 if (IS_ENABLED(CONFIG_MACH_SUNIV) &&
273 !IS_ENABLED(CONFIG_XPL_BUILD))
274 return SUNXI_BOOTED_FROM_MMC0;
275
276 if (IS_ENABLED(CONFIG_MACH_SUNIV))
277 return suniv_get_boot_source();
278 if (sunxi_egon_valid(egon_head))
279 return readb(&egon_head->boot_media);
280 if (sunxi_toc0_valid(toc0_info))
281 return readb(&toc0_info->platform[0]);
282
283 /* Not a valid image, so we must have been booted via FEL. */
284 return SUNXI_INVALID_BOOT_SOURCE;
285 }
286
287 /* The sunxi internal brom will try to loader external bootloader
288 * from mmc0, nand flash, mmc2.
289 */
sunxi_get_boot_device(void)290 uint32_t sunxi_get_boot_device(void)
291 {
292 int boot_source = sunxi_get_boot_source();
293
294 /*
295 * When booting from the SD card or NAND memory, the "eGON.BT0"
296 * signature is expected to be found in memory at the address 0x0004
297 * (see the "mksunxiboot" tool, which generates this header).
298 *
299 * When booting in the FEL mode over USB, this signature is patched in
300 * memory and replaced with something else by the 'fel' tool. This other
301 * signature is selected in such a way, that it can't be present in a
302 * valid bootable SD card image (because the BROM would refuse to
303 * execute the SPL in this case).
304 *
305 * This checks for the signature and if it is not found returns to
306 * the FEL code in the BROM to wait and receive the main u-boot
307 * binary over USB. If it is found, it determines where SPL was
308 * read from.
309 */
310 switch (boot_source) {
311 case SUNXI_INVALID_BOOT_SOURCE:
312 return BOOT_DEVICE_BOARD;
313 case SUNXI_BOOTED_FROM_MMC0:
314 case SUNXI_BOOTED_FROM_MMC0_HIGH:
315 return BOOT_DEVICE_MMC1;
316 case SUNXI_BOOTED_FROM_NAND:
317 return BOOT_DEVICE_NAND;
318 case SUNXI_BOOTED_FROM_MMC2:
319 case SUNXI_BOOTED_FROM_MMC2_HIGH:
320 return BOOT_DEVICE_MMC2;
321 case SUNXI_BOOTED_FROM_SPI:
322 return BOOT_DEVICE_SPI;
323 }
324
325 panic("Unknown boot source %d\n", boot_source);
326 return -1; /* Never reached */
327 }
328
329 #ifdef CONFIG_XPL_BUILD
sunxi_get_spl_size(void)330 uint32_t sunxi_get_spl_size(void)
331 {
332 struct boot_file_head *egon_head = (void *)SPL_ADDR;
333 struct toc0_main_info *toc0_info = (void *)SPL_ADDR;
334
335 if (sunxi_egon_valid(egon_head))
336 return readl(&egon_head->length);
337 if (sunxi_toc0_valid(toc0_info))
338 return readl(&toc0_info->length);
339
340 /* Not a valid image, so use the default U-Boot offset. */
341 return 0;
342 }
343
344 /*
345 * The eGON SPL image can be located at 8KB or at 128KB into an SD card or
346 * an eMMC device. The boot source has bit 4 set in the latter case.
347 * By adding 120KB to the normal offset when booting from a "high" location
348 * we can support both cases. The H616 has the alternative location
349 * moved up to 256 KB instead of 128KB, so cater for that, too.
350 * Also U-Boot proper is located at least 32KB after the SPL, but will
351 * immediately follow the SPL if that is bigger than that.
352 */
board_spl_mmc_get_uboot_raw_sector(struct mmc * mmc,unsigned long raw_sect)353 unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
354 unsigned long raw_sect)
355 {
356 unsigned long spl_size = sunxi_get_spl_size();
357 unsigned long sector;
358
359 sector = max(raw_sect, spl_size / 512);
360
361 switch (sunxi_get_boot_source()) {
362 case SUNXI_BOOTED_FROM_MMC0_HIGH:
363 case SUNXI_BOOTED_FROM_MMC2_HIGH:
364 sector += (128 - 8) * 2;
365 if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
366 sector += 128 * 2;
367 break;
368 }
369
370 return sector;
371 }
372
spl_boot_device(void)373 u32 spl_boot_device(void)
374 {
375 return sunxi_get_boot_device();
376 }
377
sunxi_sram_init(void)378 __weak void sunxi_sram_init(void)
379 {
380 }
381
382 /*
383 * When booting from an eMMC boot partition, the SPL puts the same boot
384 * source code into SRAM A1 as when loading the SPL from the normal
385 * eMMC user data partition: 0x2. So to know where we have been loaded
386 * from, we repeat the BROM algorithm here: checking for a valid eGON boot
387 * image at offset 0 of a (potentially) selected boot partition.
388 * If any of the conditions is not met, it must have been the eMMC user
389 * data partition.
390 */
sunxi_valid_emmc_boot(struct mmc * mmc)391 static bool sunxi_valid_emmc_boot(struct mmc *mmc)
392 {
393 struct blk_desc *bd = mmc_get_blk_desc(mmc);
394 u32 *buffer = (void *)(uintptr_t)CONFIG_TEXT_BASE;
395 struct boot_file_head *egon_head = (void *)buffer;
396 struct toc0_main_info *toc0_info = (void *)buffer;
397 int bootpart = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
398 uint32_t spl_size, emmc_checksum, chksum = 0;
399 ulong count;
400
401 /* The BROM requires BOOT_ACK to be enabled. */
402 if (!EXT_CSD_EXTRACT_BOOT_ACK(mmc->part_config))
403 return false;
404
405 /*
406 * The BOOT_BUS_CONDITION register must be 4-bit SDR, with (0x09)
407 * or without (0x01) high speed timings.
408 */
409 if ((mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x01 &&
410 (mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x09)
411 return false;
412
413 /* Partition 0 is the user data partition, bootpart must be 1 or 2. */
414 if (bootpart != EMMC_BOOT_PART_BOOT1 && bootpart != EMMC_BOOT_PART_BOOT2)
415 return false;
416
417 /* Failure to switch to the boot partition is fatal. */
418 if (mmc_switch_part(mmc, bootpart))
419 return false;
420
421 /* Read the first block to do some sanity checks on the eGON header. */
422 count = blk_dread(bd, 0, 1, buffer);
423 if (count != 1)
424 return false;
425
426 if (sunxi_egon_valid(egon_head))
427 spl_size = egon_head->length;
428 else if (sunxi_toc0_valid(toc0_info))
429 spl_size = toc0_info->length;
430 else
431 return false;
432
433 /* Read the rest of the SPL now we know it's halfway sane. */
434 count = blk_dread(bd, 1, DIV_ROUND_UP(spl_size, bd->blksz) - 1,
435 buffer + bd->blksz / 4);
436
437 /* Save the checksum and replace it with the "stamp value". */
438 emmc_checksum = buffer[3];
439 buffer[3] = 0x5f0a6c39;
440
441 /* The checksum is a simple ignore-carry addition of all words. */
442 for (count = 0; count < spl_size / 4; count++)
443 chksum += buffer[count];
444
445 debug("eMMC boot part SPL checksum: stored: 0x%08x, computed: 0x%08x\n",
446 emmc_checksum, chksum);
447
448 return emmc_checksum == chksum;
449 }
450
spl_mmc_boot_mode(struct mmc * mmc,const u32 boot_device)451 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
452 {
453 static u32 result = ~0;
454
455 if (result != ~0)
456 return result;
457
458 result = MMCSD_MODE_RAW;
459 if (!IS_SD(mmc) && IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) {
460 if (sunxi_valid_emmc_boot(mmc))
461 result = MMCSD_MODE_EMMCBOOT;
462 else
463 mmc_switch_part(mmc, 0);
464 }
465
466 debug("%s(): %s part\n", __func__,
467 result == MMCSD_MODE_RAW ? "user" : "boot");
468
469 return result;
470 }
471
board_init_f(ulong dummy)472 void board_init_f(ulong dummy)
473 {
474 sunxi_sram_init();
475
476 /* Enable non-secure access to some peripherals */
477 tzpc_init();
478
479 timer_init();
480 clock_init();
481 gpio_init();
482
483 spl_init();
484 preloader_console_init();
485
486 #if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
487 /* Needed early by sunxi_board_init if PMU is enabled */
488 i2c_init_board();
489 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
490 #endif
491 sunxi_board_init();
492 }
493 #endif /* CONFIG_XPL_BUILD */
494
495 #if !CONFIG_IS_ENABLED(SYSRESET)
reset_cpu(void)496 void reset_cpu(void)
497 {
498 #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
499 static const struct sunxi_wdog *wdog =
500 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
501
502 /* Set the watchdog for its shortest interval (.5s) and wait */
503 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
504 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
505
506 while (1) {
507 /* sun5i sometimes gets stuck without this */
508 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
509 }
510 #elif defined(CONFIG_MACH_SUN55I_A523)
511 static const void *wdog = (void *)SUNXI_TIMER_BASE;
512
513 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, wdog + WDT_SRST_REG);
514 while (1)
515 ;
516 #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
517 #if defined(CONFIG_MACH_SUN50I_H6)
518 /* WDOG is broken for some H6 rev. use the R_WDOG instead */
519 static const struct sunxi_wdog *wdog =
520 (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
521 #else
522 static const struct sunxi_wdog *wdog =
523 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
524 #endif
525 /* Set the watchdog for its shortest interval (.5s) and wait */
526 writel(WDT_CFG_RESET, &wdog->cfg);
527 writel(WDT_MODE_EN, &wdog->mode);
528 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
529 while (1) { }
530 #endif
531 }
532 #endif /* CONFIG_SYSRESET */
533
534 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A)
enable_caches(void)535 void enable_caches(void)
536 {
537 /* Enable D-cache. I-cache is already enabled in start.S */
538 dcache_enable();
539 }
540 #endif
541