Home
last modified time | relevance | path

Searched refs:which (Results 1 – 25 of 150) sorted by relevance

123456

/arch/arm/mach-aspeed/
A DKconfig24 which is enabled by support of LPC and eSPI peripherals.
36 which is enabled by support of LPC and eSPI peripherals.
/arch/arm/dts/
A Dqcs404-evb-4000-u-boot.dtsi24 /* This defines the bit clock divider which defines the baud rate.
37 * and we wind up having a reference to the XO clock which is associated
A Dfsl-sch-30842.dtsi10 * It integrates a AQR112 PHY, which supports several protocols - SGMII,
A Dfsl-sch-24801.dtsi10 * It integrates a VSC8234 quad PHY which supports 4 SGMII interfaces.
A Dfsl-sch-28021.dtsi10 * It integrates a VSC8514 quad PHY which supports 4 interfaces muxed on a
A Dns3-board.dts11 * Single mem reserve region which includes the following:
A Duniphier-ld6b.dtsi26 * which makes the pinctrl driver unshareable.
A Darmada-388.dtsi11 * property and the name of the SoC, and add the second SATA host which control
A Dfsl-sch-30841.dtsi10 * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
A Dk3-am654-base-board-u-boot.dtsi246 * which are missing for the am65x. A patch has been
263 * which are missing for the am65x. A patch has been
/arch/arm/mach-sunxi/
A Drmr_switch.S8 @ (RMR), which triggers a warm-reset of a core and can request to switch
10 @ The address at which execution starts after the reset is held in the
11 @ RVBAR system register, which is architecturally read-only.
A DKconfig154 TPR10 value from vendor DRAM settings. It tells which features
280 Select this for sunxi SoCs which have resets and clocks set up
286 Select this for sunxi SoCs which have sun6i like periphery, like
311 Select this for sunxi SoCs which uses a DRAM controller like the
312 DesignWare controller used in H3, mainly SoCs after H3, which do
643 which use a DDR3-1333 timing.
667 which use a DDR3-1333 timing.
675 which use a DDR4 timing.
683 which use an LPDDR4 timing.
783 the delay on the command lane and also phase shifts, which are
[all …]
/arch/arm/mach-imx/
A DKconfig83 activate upon a watchdog reset which is nice when iterating
95 This enables the 'dek_blob' command which is used with the
131 This option enables the priblob command which can be used
137 This enables the 'hdmidet' command which detects if an HDMI monitor
149 This is similar to kobs-ng, which is used in Linux as separate
157 which can be used has a protection feature for Manufacturing
/arch/arm/mach-renesas/
A DKconfig.rzn110 Support the Schneider RZN1D and RZN1S boards, which are based
/arch/arm/cpu/armv8/fsl-layerscape/doc/
A DREADME.pci_iommu_extra16 - for hot-plug case, specify the B.D.F with which the device will show up on
27 <addr> is the base register address of the pci controller for which the
29 <bdf> identifies to which B.D.F the action applies to
A DREADME.lsch217 the default timeout value is 128s which is the maximum. Set 10 seconds for
/arch/arm/mach-tegra/tegra124/
A DKconfig29 the Jetson TK1. The main differences are in which balls on
30 the SoC are assigned to which functions, and the PCIEe
/arch/riscv/cpu/andes/
A DKconfig17 which are provided by Andes Technology AndeStar V5 families.
/arch/arm/mach-mvebu/
A Dkwbimage.cfg.in22 # Enable BootROM output via DEBUG flag on SoCs which require it
/arch/x86/
A DKconfig11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
98 (Mobile Internet Device) platform systems which do not have
104 chipset which consume less power than most of the x86
242 Define this to boot U-Boot from a 32-bit program which sets
332 which is a very large binary blob (typically 1.5MB) which is
388 common with Intel CPUs which don't use FSP.
540 It is a binary blob which U-Boot uses to set up SDRAM.
748 Subsystem (ITSS) which is found on several Intel devices.
755 Sideband Bridge (P2SB) which is found on several Intel
809 which is not marked as reserved. For the peripherals which lose their
[all …]
/arch/arc/dts/
A Daxs10x_mb.dtsi40 * sdio_ref_clk (which comes from CGU) by 16 for
41 * default. So default mmcclk clock (which comes
/arch/sandbox/
A DKconfig70 when running test suites like the UEFI self certification test which
79 hex "Address at which to load devicetree"
/arch/mips/
A DKconfig300 The physical base address at which to map the MIPS Coherence Manager
302 the GCRs occupy a region of the physical address space which is
310 This is the base address for a memory block, which is used for
312 block which is used for loading and filling cache lines when
333 (EJTAG, SPL payload) or for machines which don't need cache initialization
334 or which want to provide their own cache implementation.
345 this can be useful on machines which don't need cache initialization or
346 which want to provide their own cache implementation.
513 Normally the initial stack frame is set up in DRAM which is often
602 Value which is inserted as boot config word 0.
[all …]
/arch/riscv/cpu/
A Du-boot-spl.lds3 * Based on arch/riscv/cpu/u-boot.lds, which is
/arch/arm/mach-versal-net/
A DKconfig32 MMU table than the one which will be allocated during

Completed in 40 milliseconds

123456