Searched refs:writeq (Results 1 – 13 of 13) sorted by relevance
| /arch/arm/lib/ |
| A D | gic-v3-its.c | 123 writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER)); in gic_lpi_tables_init()
130 writeq(val, in gic_lpi_tables_init()
151 writeq(val, (uintptr_t)(pend_base + offset)); in gic_lpi_tables_init()
157 writeq(val, (uintptr_t)(pend_base + offset)); in gic_lpi_tables_init()
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| /arch/arm/mach-socfpga/ |
| A D | spl_n5x.c | 48 writeq(0, CPU_RELEASE_ADDR); in board_init_f()
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| A D | spl_s10.c | 50 writeq(0, CPU_RELEASE_ADDR); in board_init_f()
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| A D | spl_agilex7m.c | 50 writeq(0, CPU_RELEASE_ADDR); in board_init_f()
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| A D | spl_agilex.c | 72 writeq(0, CPU_RELEASE_ADDR); in board_init_f()
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| /arch/mips/include/asm/ |
| A D | io.h | 354 #define writeq writeq in BUILDIO_MEM() macro
385 #define writeq_relaxed writeq in BUILDIO_MEM()
409 #define writeq writeq in BUILDIO_MEM() macro
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| /arch/x86/include/asm/ |
| A D | io.h | 70 #define writeq(b, addr) (*(volatile u64 *)(addr) = (b)) macro
74 #define __raw_writeq writeq
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| /arch/arm/mach-imx/imx8m/ |
| A D | psci.c | 82 writeq(entry_point, CPU_RELEASE_ADDR); in psci_cpu_on_write_entry_point()
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| /arch/sandbox/include/asm/ |
| A D | io.h | 53 #define writeq(v, addr) sandbox_write((void *)addr, v, SB_SIZE_64) macro
81 #define out_64(a,v) writeq(v,a)
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| /arch/mips/mach-octeon/ |
| A D | cpu.c | 128 writeq((u64)__cvmx_bootmem_internal_get_desc_ptr() & 0x7fffffffull, in octeon_bootmem_init()
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| /arch/arc/include/asm/ |
| A D | io.h | 193 #define writeq(v, c) ({ __iowmb(); writeq_relaxed(v, c); }) macro
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| /arch/riscv/include/asm/ |
| A D | io.h | 64 static inline void writeq(u64 val, volatile void __iomem *addr) in writeq() function
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| /arch/arm/include/asm/ |
| A D | io.h | 179 #define writeq(v, c) ({ u64 __v = v; __iowmb(); writeq_relaxed(__v, c); __v; }) macro
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