Home
last modified time | relevance | path

Searched refs:writew (Results 1 – 25 of 31) sorted by relevance

12

/arch/x86/cpu/queensbay/
A Dtnc.c126 writew(PIRQE, &rcba->d02ir); in tnc_irq_init()
127 writew(PIRQF, &rcba->d03ir); in tnc_irq_init()
128 writew(PIRQG, &rcba->d27ir); in tnc_irq_init()
129 writew(PIRQH, &rcba->d31ir); in tnc_irq_init()
130 writew(PIRQA, &rcba->d23ir); in tnc_irq_init()
131 writew(PIRQB, &rcba->d24ir); in tnc_irq_init()
132 writew(PIRQC, &rcba->d25ir); in tnc_irq_init()
133 writew(PIRQD, &rcba->d26ir); in tnc_irq_init()
/arch/sh/lib/
A Dtime_sh2.c25 writew(readw(CMSTR) | 0x01, CMSTR); in cmt_timer_start()
30 writew(readw(CMSTR) & ~0x01, CMSTR); in cmt_timer_stop()
38 writew(CMT_CMCSR_INIT, CMCSR_0); in timer_init()
42 writew(CMT_TIMER_RESET, CMCOR_0); in timer_init()
A Dtime.c28 writew(readw(TMU_BASE + TCR0) & ~TCR_TPSC, TMU_BASE + TCR0); in timer_init()
/arch/mips/mach-jz47xx/jz4780/
A Dreset.c40 writew(WDT_TCSR_PRESCALE1 | WDT_TCSR_EXT_EN, wdt_regs + WDT_TCSR); in _machine_restart()
43 writew(0, wdt_regs + WDT_TCNT); in _machine_restart()
44 writew(0, wdt_regs + WDT_TDR); in _machine_restart()
A Dtimer.c197 writew(TER_OSTEN, regs + TCU_TESR); in timer_init()
/arch/arm/cpu/arm946es/
A Dcpu.c60 writew(0x0, 0xfffece10); in reset_cpu()
61 writew(0x8, 0xfffece10); in reset_cpu()
/arch/arm/mach-imx/
A Dinit.c77 writew(0, &wdog1->wmcr); in imx_wdog_disable_powerdown()
78 writew(0, &wdog2->wmcr); in imx_wdog_disable_powerdown()
81 writew(0, &wdog3->wmcr); in imx_wdog_disable_powerdown()
83 writew(0, &wdog4->wmcr); in imx_wdog_disable_powerdown()
/arch/x86/cpu/quark/
A Dquark.c322 writew(PIRQC, &rcba->rmu_ir); in quark_irq_init()
323 writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), in quark_irq_init()
325 writew(PIRQD, &rcba->core_ir); in quark_irq_init()
326 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), in quark_irq_init()
/arch/xtensa/include/asm/
A Dio.h44 #define writew(b, addr) (void)((*(volatile unsigned short *)(addr)) = (b)) macro
51 #define __raw_writew writew
64 #define outw(val, port) writew((val), (u16 *)((unsigned long)(port)))
/arch/x86/cpu/broadwell/
A Diobp.c64 writew(IOBPU_MAGIC, RCB_REG(IOBPU)); in pch_iobp_trans_finish()
130 writew(IOBPU_MAGIC | route_id, RCB_REG(IOBPU)); in pch_iobp_exec()
/arch/arm/mach-imx/imx8m/
A Dpsci.c220 writew(wcr, &wdog->wcr); in psci_system_reset()
221 writew(wcr, &wdog->wcr); in psci_system_reset()
222 writew(wcr, &wdog->wcr); in psci_system_reset()
A Dsoc.c549 writew(enable, &wdog1->wmcr); in imx_set_wdog_powerdown()
550 writew(enable, &wdog2->wmcr); in imx_set_wdog_powerdown()
551 writew(enable, &wdog3->wmcr); in imx_set_wdog_powerdown()
1464 writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr); in reset_cpu()
/arch/microblaze/include/asm/
A Dio.h36 #define writew(b, addr) \ macro
50 #define outw(x, addr) ((void)writew(x, addr))
85 #define __raw_writew writew
/arch/arm/mach-sunxi/
A Ddram_sun55i_a523.c212 writew(low, SUNXI_DRAM_PHY0_BASE + 2); in mctl_phy_write_leveling()
213 writew(high, SUNXI_DRAM_PHY0_BASE + 4); in mctl_phy_write_leveling()
224 writew(low, SUNXI_DRAM_PHY0_BASE + 2); in mctl_phy_write_leveling()
225 writew(high, SUNXI_DRAM_PHY0_BASE + 4); in mctl_phy_write_leveling()
242 writew(low, SUNXI_DRAM_PHY0_BASE + 2); in mctl_phy_write_leveling()
243 writew(high, SUNXI_DRAM_PHY0_BASE + 4); in mctl_phy_write_leveling()
248 writew(low, SUNXI_DRAM_PHY0_BASE + 2); in mctl_phy_write_leveling()
253 writew(low, SUNXI_DRAM_PHY0_BASE + 2); in mctl_phy_write_leveling()
265 writew(low, SUNXI_DRAM_PHY0_BASE + 2); in mctl_phy_write_leveling()
271 writew(low, SUNXI_DRAM_PHY0_BASE + 2); in mctl_phy_write_leveling()
[all …]
/arch/nios2/include/asm/
A Dio.h70 #define writew(val,addr)\ macro
79 #define outw(val, addr) writew(val,addr)
/arch/x86/include/asm/
A Dio.h68 #define writew(b, addr) (*(volatile u16 *)(addr) = (b)) macro
72 #define __raw_writew writew
305 IO_COND(addr, outw(value, port), writew(value, addr)); in iowrite16()
/arch/m68k/include/asm/
A Dio.h31 #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) macro
36 #define writew(b,addr) out_be16((volatile u16 *)(addr),(b)) macro
/arch/mips/include/asm/
A Dio.h352 #define writew writew in BUILDIO_MEM() macro
383 #define writew_relaxed writew in BUILDIO_MEM()
/arch/sh/include/asm/
A Dio.h153 #define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c)) macro
186 #define writew(v, addr) __raw_writew(v, addr) macro
/arch/arm/mach-omap2/
A Dhwinit-common.c35 writew(pad->val, base + pad->offset); in do_set_mux()
/arch/x86/cpu/ivybridge/
A Dsdram.c397 writew(0x0100, RCB_REG(OIC)); in rcba_config()
557 writew(0xCAFE, MCHBAR_REG(SSKPD)); in dram_init()
/arch/powerpc/include/asm/
A Dio.h31 #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) macro
36 #define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) macro
/arch/sandbox/include/asm/
A Dio.h50 #define writew(v, addr) sandbox_write((void *)addr, v, SB_SIZE_16) macro
83 #define out_16(a,v) writew(v,a)
/arch/arm/mach-imx/mx7/
A Dsoc.c429 writew(reg, &wdog->wcr); in set_wdog_reset()
/arch/arm/include/asm/arch-omap3/
A Dmux.h493 writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));

Completed in 71 milliseconds

12