| /arch/arm/cpu/armv8/ |
| A D | cache.S | 41 add x2, x2, #4 /* x2 <- log2(cache line size) */
54 lsl x7, x4, x2
176 mov x2, #4
177 lsl x2, x2, x3 /* cache line size */
180 sub x3, x2, #1
183 add x0, x0, x2
202 mov x2, #4
203 lsl x2, x2, x3 /* cache line size */
206 sub x3, x2, #1
209 add x0, x0, x2
[all …]
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| A D | fel_utils.S | 36 adr x2, fel_stash
37 str w0, [x2]
38 str w1, [x2, #4]
47 str w0, [x2], #0x4
50 str w0, [x2], #0x4
53 str w0, [x2, #0x8]
56 str w0, [x2]
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| A D | acpi_park_v8.S | 50 mrs x2, mpidr_el1
51 lsr x9, x2, #32
52 bfi x2, x9, #24, #8 /* w2 is aff3:aff2:aff1:aff0 */
74 add x2, x0, #ACPI_PP_CPU_CODE_OFFSET
77 br x2
88 mov x2, #ACPI_PP_JMP_ADR_INVALID
103 cmp x1, x2
107 str x2, [x0, #ACPI_PP_CPU_JMP_OFFSET]
|
| A D | exceptions.S | 62 stp x1, x2, [sp, #-16]!
79 mrs x2, elr_el3
83 mrs x2, elr_el2
87 mrs x2, elr_el1
91 stp x3, x2, [sp, #-16]!
105 ldp xzr, x2, [sp],#16
107 3: msr elr_el3, x2
109 2: msr elr_el2, x2
111 1: msr elr_el1, x2
126 ldp x1, x2, [sp],#16
|
| A D | sec_firmware_asm.S | 33 str w3, [x2]
47 mov x2, 0x0
68 mov x3, x2
69 mov x2, x1
|
| /arch/arm/lib/ |
| A D | relocate_64.S | 48 adrp x2, __image_copy_end /* x2 <- address bits [31:12] */
49 add x2, x2, :lo12:__image_copy_end /* x2 <- address bits [11:00] */
53 cmp x1, x2 /* until source end address [x2] */
60 adrp x2, __rel_dyn_start /* x2 <- address bits [31:12] */
61 add x2, x2, :lo12:__rel_dyn_start /* x2 <- address bits [11:00] */
65 ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */
66 ldr x4, [x2], #8 /* x4 <- addend */
76 cmp x2, x3
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| A D | setjmp_aarch64.S | 19 mov x2, sp
20 str x2, [x0, #96]
34 ldr x2, [x0,#96]
35 mov sp, x2
46 add x2, x2, x3
47 stp x1, x2, [x0,#88]
|
| /arch/arm/cpu/armv8/bcmns3/ |
| A D | lowlevel.S | 25 ldr x2, [x0]
26 cmp x2, x1 /* check status */
49 ldr x2, [x0]
50 and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
51 orr x2, x2, x1
52 str x2, [x0]
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| /arch/arm/include/asm/arch-qemu-sbsa/ |
| A D | boot0.h | 10 ldr x2, _TEXT_BASE /* x2 <- Linked value of _start */
11 subs x9, x1, x2 /* x9 <- Run-vs-link offset */
22 stp x10, x11, [x2], #16 /* copy to target address [x2] */
27 ldr x2, _TEXT_BASE /* x2 <- Linked value of _start */
28 br x2 /* Jump to linked address */
|
| /arch/arm/dts/ |
| A D | rk3288-veyron-mickey-u-boot.dtsi | 6 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
9 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
12 0x0 0xc3 0x6 0x2>;
|
| A D | armada-7040-db-nand.dts | 79 pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
80 0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
82 0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0
|
| A D | rk3288-rock-pi-n8-u-boot.dtsi | 15 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
18 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
21 0x0 0xc3 0x6 0x2>;
|
| A D | rk3288-evb-u-boot.dtsi | 9 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
12 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
15 0x0 0xc3 0x6 0x2>;
|
| A D | rk3288-veyron-minnie-u-boot.dtsi | 6 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
9 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
|
| A D | t8103.dtsi | 44 reg = <0x0 0x2>;
124 reg = <0x2 0x35010000 0x0 0x4000>;
137 reg = <0x2 0x35014000 0x0 0x4000>;
150 reg = <0x2 0x35018000 0x0 0x4000>;
164 reg = <0x2 0x3501c000 0x0 0x4000>;
177 reg = <0x2 0x35020000 0x0 0x4000>;
243 reg = <0x2 0x3b700000 0 0x14000>;
308 reg = <0x2 0x3d0d9300 0x0 0x100>;
342 reg = <0x2 0x3d280000 0 0x4000>;
440 <0x2 0x77400000 0x0 0x4000>;
[all …]
|
| A D | rk3288-veyron-speedy-u-boot.dtsi | 23 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
26 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
|
| A D | rk3288-tinker-u-boot.dtsi | 9 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
12 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
15 0x0 0xc3 0x6 0x2>;
|
| /arch/arm/cpu/armv8/fsl-layerscape/ |
| A D | lowlevel.S | 39 ldr x2, =DCFG_CCSR_SVR
40 ldr w2, [x2]
49 ldr x2, =SCFG_GIC400_ALIGN
50 ldr w2, [x2]
330 mov x2, #0
332 str x2, [x0]
368 ldr x2, [x0]
386 ldr x2, [x0]
387 and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
388 orr x2, x2, x1
[all …]
|
| /arch/riscv/dts/ |
| A D | qilai-voyager.dts | 9 #address-cells = <0x2>;
10 #size-cells = <0x2>;
77 reg = <0x2>;
124 cache-level = <0x2>;
139 #address-cells = <0x2>;
140 #size-cells = <0x2>;
146 #address-cells = <0x2>;
147 #interrupt-cells = <0x2>;
159 #address-cells = <0x2>;
160 #interrupt-cells = <0x2>;
[all …]
|
| /arch/arm/mach-mediatek/mt7981/ |
| A D | lowlevel_init.S | 26 mov x3, x2
27 mov x2, x1
|
| /arch/arm/mach-mediatek/mt7987/ |
| A D | lowlevel_init.S | 24 mov x3, x2
25 mov x2, x1
|
| /arch/arm/mach-mediatek/mt7988/ |
| A D | lowlevel_init.S | 24 mov x3, x2
25 mov x2, x1
|
| /arch/arm/mach-mediatek/mt8518/ |
| A D | lowlevel_init.S | 23 mov x3, x2
24 mov x2, x1
|
| /arch/arm/mach-mediatek/mt7986/ |
| A D | lowlevel_init.S | 26 mov x3, x2
27 mov x2, x1
|
| /arch/arm/mach-mediatek/mt8512/ |
| A D | lowlevel_init.S | 23 mov x3, x2
24 mov x2, x1
|