Searched refs:zq (Results 1 – 14 of 14) sorted by relevance
| /arch/arm/mach-sunxi/ |
| A D | dram_sun50i_h6.c | 488 clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val); in mctl_channel_init()
489 clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff, in mctl_channel_init()
491 clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff); in mctl_channel_init()
492 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff); in mctl_channel_init()
493 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100); in mctl_channel_init()
494 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4); in mctl_channel_init()
495 clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff); in mctl_channel_init()
496 setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff); in mctl_channel_init()
497 setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100); in mctl_channel_init()
498 setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4); in mctl_channel_init()
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| A D | dram_sun8i_a23.c | 33 .zq = CONFIG_DRAM_ZQ,
230 writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1); in mctl_init()
237 writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); in mctl_init()
247 writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); in mctl_init()
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| A D | dram_sun9i.c | 696 clrsetbits_le32(&mctl_phy->zq[0].pr, 0xff, in mctl_channel_init()
698 clrsetbits_le32(&mctl_phy->zq[1].pr, 0xff, in mctl_channel_init()
700 clrsetbits_le32(&mctl_phy->zq[2].pr, 0xff, in mctl_channel_init()
726 writel(0x04058D02, &mctl_phy->zq[0].cr); /* CK/CA */ in mctl_channel_init()
727 writel(0x04058D02, &mctl_phy->zq[1].cr); /* DX0/DX1 */ in mctl_channel_init()
728 writel(0x04058D02, &mctl_phy->zq[2].cr); /* DX2/DX3 */ in mctl_channel_init()
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| A D | dram_sunxi_dw.c | 336 u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; in mctl_h3_zq_calibration_quirk() local
338 writel((zq << 20) | (zq << 16) | (zq << 12) | in mctl_h3_zq_calibration_quirk()
339 (zq << 8) | (zq << 4) | (zq << 0), in mctl_h3_zq_calibration_quirk()
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| A D | dram_sun4i.c | 511 static void mctl_set_impedance(u32 zq, bool odt_en) in mctl_set_impedance() argument
515 u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF; in mctl_set_impedance()
623 mctl_set_impedance(para->zq, para->odt_en); in dramc_init_helper()
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| A D | Kconfig | 744 int "sunxi dram zq value"
756 Set the dram zq value.
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| /arch/arm/mach-uniphier/dram/ |
| A D | cmd_ddrmphy.c | 96 int phy, zq, i; in zq_dump() local
105 for (zq = 0; zq < param->phy[phy].nr_zq; zq++) { in zq_dump()
106 printf("PHY%dZQ%d:", phy, zq); in zq_dump()
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| A D | umc-pxs2.c | 149 int zq, dx; in ddrphy_init() local
209 for (zq = 0; zq < 4; zq++) { in ddrphy_init()
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| /arch/arm/mach-omap2/ |
| A D | emif-common.c | 781 u32 zq = 0, val = 0; in get_zq_config_reg() local
790 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT; in get_zq_config_reg()
792 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT; in get_zq_config_reg()
794 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT; in get_zq_config_reg()
796 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT; in get_zq_config_reg()
806 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT; in get_zq_config_reg()
808 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT; in get_zq_config_reg()
810 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT; in get_zq_config_reg()
812 return zq; in get_zq_config_reg()
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| /arch/arm/dts/ |
| A D | k3-am654-ddr.dtsi | 199 ti,phy-zq = <
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| /arch/arm/include/asm/arch-sunxi/ |
| A D | dram_sun4i.h | 76 u32 zq; member
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| A D | dram_sun9i.h | 142 } zq[4]; /* 0x240, 0x250, 0x260, 0x270 */ member
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| A D | dram_sun50i_h6.h | 242 } zq[2]; /* 0x680, 0x6a0 */ member
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| A D | dram_sun8i_a23.h | 19 u32 zq; member
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