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Searched refs:zq_mode_dds (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init.h116 unsigned zq_mode_dds; member
A Ddmc_common.c30 val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT; in dmc_config_zq()
A Dclock_init_exynos5.c218 .zq_mode_dds = 0x7,
321 .zq_mode_dds = 0x7,
424 .zq_mode_dds = 0x5,

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