1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9 *
10 * (C) Copyright 2003
11 * Texas Instruments, <www.ti.com>
12 * Kshitij Gupta <Kshitij@ti.com>
13 *
14 * (C) Copyright 2004
15 * ARM Ltd.
16 * Philippe Robin, <philippe.robin@arm.com>
17 */
18
19 #include <config.h>
20 #include <bootstage.h>
21 #include <cpu_func.h>
22 #include <dm.h>
23 #include <env.h>
24 #include <init.h>
25 #include <net.h>
26 #include <netdev.h>
27 #include <armcoremodule.h>
28 #include <asm/global_data.h>
29 #include <asm/io.h>
30 #include <dm/platform_data/serial_pl01x.h>
31 #include "arm-ebi.h"
32 #include "integrator-sc.h"
33 #include <asm/mach-types.h>
34
35 DECLARE_GLOBAL_DATA_PTR;
36
37 static const struct pl01x_serial_plat serial_plat = {
38 .base = 0x16000000,
39 #ifdef CONFIG_ARCH_CINTEGRATOR
40 .type = TYPE_PL011,
41 .clock = 14745600,
42 #else
43 .type = TYPE_PL010,
44 .clock = 0, /* Not used for PL010 */
45 #endif
46 };
47
48 U_BOOT_DRVINFO(integrator_serials) = {
49 .name = "serial_pl01x",
50 .plat = &serial_plat,
51 };
52
53 void peripheral_power_enable (void);
54
55 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
show_boot_progress(int progress)56 void show_boot_progress(int progress)
57 {
58 printf("Boot reached stage %d\n", progress);
59 }
60 #endif
61
62 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
63
64 /*
65 * Miscellaneous platform dependent initialisations
66 */
67
board_init(void)68 int board_init (void)
69 {
70 u32 val;
71
72 /* arch number of Integrator Board */
73 #ifdef CONFIG_ARCH_CINTEGRATOR
74 gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
75 #else
76 gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
77 #endif
78
79 /* adress of boot parameters */
80 gd->bd->bi_boot_params = 0x00000100;
81
82 #ifdef CONFIG_CM_REMAP
83 extern void cm_remap(void);
84 cm_remap(); /* remaps writeable memory to 0x00000000 */
85 #endif
86
87 #ifdef CONFIG_ARCH_CINTEGRATOR
88 /*
89 * Flash protection on the Integrator/CP is in a simple register
90 */
91 val = readl(CP_FLASHPROG);
92 val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
93 writel(val, CP_FLASHPROG);
94 #else
95 /*
96 * The Integrator/AP has some special protection mechanisms
97 * for the external memories, first the External Bus Interface (EBI)
98 * then the system controller (SC).
99 *
100 * The system comes up with the flash memory non-writable and
101 * configuration locked. If we want U-Boot to be used for flash
102 * access we cannot have the flash memory locked.
103 */
104 writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
105 val = readl(EBI_BASE + EBI_CSR1_REG);
106 val &= EBI_CSR_WREN_MASK;
107 val |= EBI_CSR_WREN_ENABLE;
108 writel(val, EBI_BASE + EBI_CSR1_REG);
109 writel(0, EBI_BASE + EBI_LOCK_REG);
110
111 /*
112 * Set up the system controller to remove write protection from
113 * the flash memory and enable Vpp
114 */
115 writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
116 #endif
117
118 icache_enable();
119
120 return 0;
121 }
122
misc_init_r(void)123 int misc_init_r (void)
124 {
125 env_set("verify", "n");
126 return (0);
127 }
128
129 /*
130 * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
131 * from there, which means we cannot test the RAM underneath the ROM at this
132 * point. It will be unmapped later on, when we are executing from the
133 * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
134 * RAM on higher addresses works fine.
135 */
136 #define REMAPPED_FLASH_SZ 0x40000
137
dram_init(void)138 int dram_init (void)
139 {
140 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
141 #ifdef CONFIG_CM_SPD_DETECT
142 {
143 extern void dram_query(void);
144 u32 cm_reg_sdram;
145 u32 sdram_shift;
146
147 dram_query(); /* Assembler accesses to CM registers */
148 /* Queries the SPD values */
149
150 /* Obtain the SDRAM size from the CM SDRAM register */
151
152 cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
153 /* Register SDRAM size
154 *
155 * 0xXXXXXXbbb000bb 16 MB
156 * 0xXXXXXXbbb001bb 32 MB
157 * 0xXXXXXXbbb010bb 64 MB
158 * 0xXXXXXXbbb011bb 128 MB
159 * 0xXXXXXXbbb100bb 256 MB
160 *
161 */
162 sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
163 gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE +
164 REMAPPED_FLASH_SZ,
165 0x01000000 << sdram_shift);
166 }
167 #else
168 gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE +
169 REMAPPED_FLASH_SZ,
170 PHYS_SDRAM_1_SIZE);
171 #endif /* CM_SPD_DETECT */
172 /* We only have one bank of RAM, set it to whatever was detected */
173 gd->bd->bi_dram[0].size = gd->ram_size;
174
175 return 0;
176 }
177
178 #ifdef CONFIG_CMD_NET
board_eth_init(struct bd_info * bis)179 int board_eth_init(struct bd_info *bis)
180 {
181 int rc = 0;
182 return rc;
183 }
184 #endif
185