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Searched refs:CTRLMMR_USB0_PHY_CTRL (Results 1 – 5 of 5) sorted by relevance

/board/phytec/phycore_am62ax/
A Dphycore-am62ax.c24 #define CTRLMMR_USB0_PHY_CTRL 0x43004008 macro
34 val = readl(CTRLMMR_USB0_PHY_CTRL); in spl_board_init()
36 writel(val, CTRLMMR_USB0_PHY_CTRL); in spl_board_init()
/board/toradex/verdin-am62/
A Dverdin-am62.c106 #define CTRLMMR_USB0_PHY_CTRL 0x43004008 macro
118 val = readl(CTRLMMR_USB0_PHY_CTRL); in spl_board_init()
120 writel(val, CTRLMMR_USB0_PHY_CTRL); in spl_board_init()
/board/phytec/phycore_am64x/
A Dphycore-am64x.c130 #define CTRLMMR_USB0_PHY_CTRL 0x43004008 macro
139 val = readl(CTRLMMR_USB0_PHY_CTRL); in spl_board_init()
141 writel(val, CTRLMMR_USB0_PHY_CTRL); in spl_board_init()
/board/ti/am64x/
A Devm.c216 #define CTRLMMR_USB0_PHY_CTRL 0x43004008 macro
224 val = readl(CTRLMMR_USB0_PHY_CTRL); in spl_board_init()
226 writel(val, CTRLMMR_USB0_PHY_CTRL); in spl_board_init()
/board/phytec/phycore_am62x/
A Dphycore-am62x.c211 #define CTRLMMR_USB0_PHY_CTRL 0x43004008 macro
221 val = readl(CTRLMMR_USB0_PHY_CTRL); in spl_board_init()
223 writel(val, CTRLMMR_USB0_PHY_CTRL); in spl_board_init()

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