| /board/freescale/ls1021atsn/ |
| A D | ls1021atsn.c | 34 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
36 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
37 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
48 out_be32(&ddr->sdram_cfg_2, in ddrmc_init()
51 out_be32(&ddr->init_ext_addr, (1 << 31)); in ddrmc_init()
54 out_be32(&ddr->ddr_cdr2, in ddrmc_init()
60 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); in ddrmc_init()
63 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); in ddrmc_init()
73 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); in ddrmc_init()
81 tmp = in_be32(&ddr->debug[28]); in ddrmc_init()
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| /board/freescale/ls1021aiot/ |
| A D | ls1021aiot.c | 57 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
59 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
60 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
62 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
69 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); in ddrmc_init()
70 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); in ddrmc_init()
72 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); in ddrmc_init()
82 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); in ddrmc_init()
85 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); in ddrmc_init()
90 tmp = in_be32(&ddr->debug[28]); in ddrmc_init()
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| /board/socrates/ |
| A D | sdram.c | 27 struct ccsr_ddr __iomem *ddr = in fixed_sdram() local
33 ddr->cs0_config = 0; in fixed_sdram()
34 ddr->sdram_cfg = 0; in fixed_sdram()
36 ddr->cs0_bnds = CFG_SYS_DDR_CS0_BNDS; in fixed_sdram()
37 ddr->cs0_config = CFG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
38 ddr->timing_cfg_0 = CFG_SYS_DDR_TIMING_0; in fixed_sdram()
39 ddr->timing_cfg_1 = CFG_SYS_DDR_TIMING_1; in fixed_sdram()
40 ddr->timing_cfg_2 = CFG_SYS_DDR_TIMING_2; in fixed_sdram()
41 ddr->sdram_mode = CFG_SYS_DDR_MODE; in fixed_sdram()
43 ddr->sdram_cfg_2 = CFG_SYS_DDR_CONFIG_2; in fixed_sdram()
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| /board/gdsys/mpc8308/ |
| A D | sdram.c | 45 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
49 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
52 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); in fixed_sdram()
53 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); in fixed_sdram()
54 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); in fixed_sdram()
55 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); in fixed_sdram()
57 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
58 out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
59 out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); in fixed_sdram()
60 out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); in fixed_sdram()
[all …]
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| /board/freescale/mpc837xerdb/ |
| A D | mpc837xerdb.c | 113 im->ddr.cs_config[0] = CFG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
116 im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0; in fixed_sdram()
117 im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1; in fixed_sdram()
118 im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2; in fixed_sdram()
119 im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3; in fixed_sdram()
120 im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
121 im->ddr.sdram_cfg2 = CFG_SYS_DDR_SDRAM_CFG2; in fixed_sdram()
122 im->ddr.sdram_mode = CFG_SYS_DDR_MODE; in fixed_sdram()
123 im->ddr.sdram_mode2 = CFG_SYS_DDR_MODE2; in fixed_sdram()
124 im->ddr.sdram_interval = CFG_SYS_DDR_INTERVAL; in fixed_sdram()
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| /board/freescale/ls1021atwr/ |
| A D | ls1021atwr.c | 149 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
151 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
152 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
163 out_be32(&ddr->sdram_cfg_2, in ddrmc_init()
166 out_be32(&ddr->init_ext_addr, (1 << 31)); in ddrmc_init()
169 out_be32(&ddr->ddr_cdr2, in ddrmc_init()
175 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); in ddrmc_init()
178 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); in ddrmc_init()
188 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); in ddrmc_init()
196 tmp = in_be32(&ddr->debug[28]); in ddrmc_init()
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| /board/keymile/km83xx/ |
| A D | km83xx.c | 217 out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
218 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); in fixed_sdram()
219 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); in fixed_sdram()
220 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); in fixed_sdram()
221 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); in fixed_sdram()
222 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
223 out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
224 out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); in fixed_sdram()
225 out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); in fixed_sdram()
229 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in fixed_sdram()
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| /board/cssi/cmpcpro/ |
| A D | cmpcpro.c | 303 out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL); in dram_init()
305 out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); in dram_init()
307 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); in dram_init()
308 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); in dram_init()
309 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); in dram_init()
310 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); in dram_init()
311 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); in dram_init()
312 out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); in dram_init()
313 out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); in dram_init()
314 out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); in dram_init()
[all …]
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| /board/freescale/ls1028a/ |
| A D | Makefile | 8 obj-y += ddr.o
|
| /board/freescale/ls2080ardb/ |
| A D | Makefile | 6 obj-y += ddr.o
|
| /board/ti/j784s4/ |
| A D | MAINTAINERS | 12 F: arch/arm/dts/k3-j784s4-ddr.dtsi
13 F: arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
27 F: arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi
30 F: arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi
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| /board/freescale/ls2080aqds/ |
| A D | Makefile | 6 obj-y += ddr.o
|
| /board/freescale/ls1046afrwy/ |
| A D | Makefile | 5 obj-y += ddr.o
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| /board/freescale/ls1021aqds/ |
| A D | Makefile | 8 obj-y += ddr.o
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| /board/freescale/ls1046aqds/ |
| A D | Makefile | 7 obj-y += ddr.o
|
| /board/freescale/mpc8548cds/ |
| A D | Makefile | 8 obj-y += ddr.o
|
| /board/freescale/p2041rdb/ |
| A D | Makefile | 9 obj-y += ddr.o
|
| /board/freescale/ls1043aqds/ |
| A D | Makefile | 7 obj-y += ddr.o
|
| /board/imgtec/boston/ |
| A D | Makefile | 6 obj-y += ddr.o
|
| /board/compulab/imx8mm-cl-iot-gate/ddr/ |
| A D | Makefile | 1 obj-y += ddr.o
|
| /board/technexion/pico-imx8mq/ |
| A D | spl.c | 53 u8 ddr = 0, size; in spl_dram_init() local
64 ddr |= !!gpio_get_value(DDR_DET_3) << 0; in spl_dram_init()
65 ddr |= !!gpio_get_value(DDR_DET_2) << 1; in spl_dram_init()
66 ddr |= !!gpio_get_value(DDR_DET_1) << 2; in spl_dram_init()
68 switch (ddr) { in spl_dram_init()
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| /board/phytium/pe2201/ |
| A D | Makefile | 11 obj-y += ddr.o
|
| /board/phytium/pomelo/ |
| A D | Makefile | 11 obj-y += ddr.o
|
| /board/beacon/imx8mm/ |
| A D | imximage-8mm-lpddr4.cfg | 8 LOADER u-boot-spl-ddr.bin 0x7E1000
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| /board/toradex/verdin-imx8mm/ |
| A D | imximage.cfg | 8 LOADER u-boot-spl-ddr.bin 0x7e1000
|