| /board/renesas/common/ |
| A D | gen3-common.c | 140 int offset, enabled; in update_rpc_status() local
153 enabled = fdtdec_get_is_enabled(atf_fdt_blob, offset); in update_rpc_status()
154 if (!enabled) in update_rpc_status()
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| /board/bsh/imx6ulz_smm_m2/ |
| A D | Kconfig | 22 If this option is enabled, U-Boot will be configured to support
28 If this option is enabled, U-Boot will be configured to support
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| /board/LaCie/net2big_v2/ |
| A D | kwbimage.cfg | 36 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
108 # bit7 : 1 , D2P Latency enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
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| /board/LaCie/netspace_v2/ |
| A D | kwbimage-is2.cfg | 36 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
108 # bit7 : 1 , D2P Latency enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
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| A D | kwbimage-ns2l.cfg | 36 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
108 # bit7 : 1 , D2P Latency enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
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| A D | kwbimage.cfg | 36 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
108 # bit7 : 1 , D2P Latency enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
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| /board/Marvell/dreamplug/ |
| A D | kwbimage.cfg | 36 # bit18: 1=cpu lock transaction enabled
76 # bit0: 0, OpenPage enabled
94 # bit0: 0, DDR DLL enabled
100 # bit10: 0, differential DQS enabled
102 # bit12: 0, DDR output buffer enabled
112 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
122 # bit0: 1, Window enabled
129 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
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| /board/Marvell/guruplug/ |
| A D | kwbimage.cfg | 35 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
128 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
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| /board/Marvell/sheevaplug/ |
| A D | kwbimage.cfg | 35 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
128 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
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| /board/Seagate/nas220/ |
| A D | kwbimage.cfg | 40 # bit18: 1=cpu lock transaction enabled
80 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
105 # bit10: 0, differential DQS enabled
107 # bit12: 0, DDR output buffer enabled
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
123 # bit0: 1, Window enabled
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| /board/Marvell/openrd/ |
| A D | kwbimage.cfg | 35 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
128 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
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| /board/cloudengines/pogo_v4/ |
| A D | kwbimage.cfg | 36 # bit18: 1=cpu lock transaction enabled
76 # bit0: 0, OpenPage enabled
94 # bit0: 0, DDR DLL enabled
100 # bit10: 0, differential DQS enabled
102 # bit12: 0, DDR output buffer enabled
112 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
122 # bit0: 1, Window enabled
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| /board/Seagate/dockstar/ |
| A D | kwbimage.cfg | 38 # bit18: 1=cpu lock transaction enabled
78 # bit0: 0, OpenPage enabled
96 # bit0: 0, DDR DLL enabled
102 # bit10: 0, differential DQS enabled
104 # bit12: 0, DDR output buffer enabled
114 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
124 # bit0: 1, Window enabled
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| /board/Seagate/goflexhome/ |
| A D | kwbimage.cfg | 41 # bit18: 1=cpu lock transaction enabled
81 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
105 # bit10: 0, differential DQS enabled
107 # bit12: 0, DDR output buffer enabled
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
127 # bit0: 1, Window enabled
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| /board/Synology/ds109/ |
| A D | kwbimage.cfg | 39 # bit18: 1=cpu lock transaction enabled
79 # bit0: 0, OpenPage enabled
97 # bit0: 0, DDR DLL enabled
103 # bit10: 0, differential DQS enabled
105 # bit12: 0, DDR output buffer enabled
115 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
125 # bit0: 1, Window enabled
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| /board/d-link/dns325/ |
| A D | kwbimage.cfg | 44 # bit18: 1, cpu lock transaction enabled
85 # bit0: 0, OPEn=OpenPage enabled
103 # bit0: 0, DRAM DLL enabled
109 # bit10: 0, differential DQS enabled
111 # bit12: 0, DRAM output buffer enabled
121 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
143 # bit0: 1, Window enabled
150 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
151 # bit0: 1, Window enabled
179 # bit14: 1, M_STARTBURST_IN ODT enabled
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| /board/raidsonic/ib62x0/ |
| A D | kwbimage.cfg | 36 # bit18: 0x1, cpu lock transaction enabled
76 # bit0: 0, OpenPage enabled
94 # bit0: 0, DDR DLL enabled
100 # bit10: 0, differential DQS enabled
102 # bit12: 0, DDR output buffer enabled
112 # bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
122 # bit0: 0x1, Window enabled
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| /board/iomega/iconnect/ |
| A D | kwbimage.cfg | 35 # bit18: 0x1, cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
111 # bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 0x1, Window enabled
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| /board/cloudengines/pogo_e02/ |
| A D | kwbimage.cfg | 39 # bit18: 1=cpu lock transaction enabled
79 # bit0: 0, OpenPage enabled
97 # bit0: 0, DDR DLL enabled
103 # bit10: 0, differential DQS enabled
105 # bit12: 0, DDR output buffer enabled
115 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
125 # bit0: 1, Window enabled
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| /board/buffalo/lsxl/ |
| A D | kwbimage-lschl.cfg | 46 # bit18: 1, cpu lock transaction enabled
91 # bit0: 0, OPEn=OpenPage enabled
112 # bit0: 0, DRAM DLL enabled
118 # bit10: 0, differential DQS enabled
120 # bit12: 0, DRAM output buffer enabled
131 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
159 # bit0: 1, Window enabled
199 # bit14: 1, M_STARTBURST_IN ODT enabled
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| A D | kwbimage-lsxhl.cfg | 46 # bit18: 1, cpu lock transaction enabled
91 # bit0: 0, OPEn=OpenPage enabled
112 # bit0: 0, DRAM DLL enabled
118 # bit10: 0, differential DQS enabled
120 # bit12: 0, DRAM output buffer enabled
131 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
159 # bit0: 1, Window enabled
199 # bit14: 1, M_STARTBURST_IN ODT enabled
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| /board/raspberrypi/rpi/ |
| A D | rpi.c | 645 bool enabled; in acpi_rpi_board_fill_ssdt() local
675 enabled = false; in acpi_rpi_board_fill_ssdt()
695 enabled = (node > 0) ? fdtdec_get_is_enabled(gd->fdt_blob, node) : 0; in acpi_rpi_board_fill_ssdt()
698 acpigen_write_name_integer(ctx, "_STA", enabled ? 0xf : 0); in acpi_rpi_board_fill_ssdt()
708 enabled = (node > 0) ? fdtdec_get_is_enabled(gd->fdt_blob, node) : 0; in acpi_rpi_board_fill_ssdt()
709 acpigen_write_name_integer(ctx, "_STA", enabled ? 0xf : 0); in acpi_rpi_board_fill_ssdt()
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| /board/freescale/p1_p2_rdb_pc/ |
| A D | README | 40 CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
56 enabled in relative defconfig file,
62 If device tree support is enabled in defconfig,
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| /board/google/chromebook_coral/ |
| A D | Kconfig | 33 With this option enabled, the EC console can be used to watch post
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| /board/xilinx/zynq/ |
| A D | Kconfig | 30 and authentication feature enabled while generating
|