Searched refs:timing (Results 1 – 13 of 13) sorted by relevance
| /board/samsung/common/ |
| A D | sromc.c | 27 u32 timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */ in exyno5_sromc_probe() local
44 ret = dev_read_u32_array(dev, "srom-timing", timing, in exyno5_sromc_probe()
50 smc_bc_conf = SROMC_BC_TACS(timing[FDT_SROM_TACS]) | in exyno5_sromc_probe()
51 SROMC_BC_TCOS(timing[FDT_SROM_TCOS]) | in exyno5_sromc_probe()
52 SROMC_BC_TACC(timing[FDT_SROM_TACC]) | in exyno5_sromc_probe()
53 SROMC_BC_TCOH(timing[FDT_SROM_TCOH]) | in exyno5_sromc_probe()
54 SROMC_BC_TAH(timing[FDT_SROM_TAH]) | in exyno5_sromc_probe()
55 SROMC_BC_TACP(timing[FDT_SROM_TACP]) | in exyno5_sromc_probe()
56 SROMC_BC_PMC(timing[FDT_SROM_PMC]); in exyno5_sromc_probe()
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| /board/compulab/imx8mm-cl-iot-gate/ddr/ |
| A D | ddr.c | 41 struct dram_timing_info *timing; member
48 .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
50 .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
52 .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
54 .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
56 .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
58 .size = 2048, .count = 1, .timing = &ucm_dram_timing_ff020008},
60 .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
154 if (ddr_init(lpddr4_array[i].timing)) { in spl_dram_init_compulab()
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| /board/friendlyarm/nanopi2/ |
| A D | lcds.c | 100 .timing = {
127 .timing = {
154 .timing = {
181 .timing = {
208 .timing = {
235 .timing = {
262 .timing = {
288 .timing = {
315 .timing = {
341 .timing = {
[all …]
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| A D | board.c | 131 struct nxp_lcd_timing *timing = &lcd->timing; in nx_display_fixup_dp() local
139 sync->h_sync_width = timing->h_sw; in nx_display_fixup_dp()
140 sync->h_back_porch = timing->h_bp; in nx_display_fixup_dp()
141 sync->h_front_porch = timing->h_fp; in nx_display_fixup_dp()
145 sync->v_sync_width = timing->v_sw; in nx_display_fixup_dp()
146 sync->v_back_porch = timing->v_bp; in nx_display_fixup_dp()
147 sync->v_front_porch = timing->v_fp; in nx_display_fixup_dp()
151 div = timing->h_sw + timing->h_bp + timing->h_fp + lcd->width; in nx_display_fixup_dp()
152 div *= timing->v_sw + timing->v_bp + timing->v_fp + lcd->height; in nx_display_fixup_dp()
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| A D | nxp-fb.h | 69 struct nxp_lcd_timing timing; member
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| /board/freescale/imx91_evk/ |
| A D | Kconfig | 17 Select the LPDDR4 timing and 1.1V VDDQ
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| /board/freescale/imx93_evk/ |
| A D | Kconfig | 17 Select the LPDDR4X timing and 0.6V VDDQ
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| /board/freescale/p1_p2_rdb_pc/ |
| A D | README | 25 to timing data embedded in the source code will be used. Raw timing data is
31 for writing timing.
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| A D | ddr.c | 186 #error Missing raw timing data for this board
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| /board/imgtec/ci20/ |
| A D | ci20.c | 265 .timing = {
309 .timing = {
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| /board/buffalo/lsxl/ |
| A D | kwbimage-lschl.cfg | 20 # not further specified in HW manual, timing taken from original vendor port
24 # not further specified in HW manual, timing taken from original vendor port
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| A D | kwbimage-lsxhl.cfg | 20 # not further specified in HW manual, timing taken from original vendor port
24 # not further specified in HW manual, timing taken from original vendor port
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| /board/tbs/tbs2910/ |
| A D | tbs2910.cfg | 88 /* ODT timing */
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