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Searched refs:value (Results 1 – 25 of 148) sorted by relevance

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/board/aspeed/ibex_ast2700/
A Dsli.c20 uint32_t value; in sli_wait() local
25 value = readl((void *)base + SLI_INTR_STATUS); in sli_wait()
26 if (value & SLI_INTR_RX_ERRORS) in sli_wait()
28 } while ((value & mask) != mask); in sli_wait()
48 uint32_t value; in sli_init() local
52 if (value) in sli_init()
56 value = readl((void *)SLIH_IOD_BASE + SLI_CTRL_III); in sli_init()
57 value = FIELD_GET(SLI_CLK_SEL, value); in sli_init()
58 if (value) { in sli_init()
65 writel(value, (void *)SLIH_IOD_BASE + SLI_CTRL_I); in sli_init()
[all …]
/board/samsung/smdkc100/
A Donenand.c23 int value; in onenand_board_init() local
29 value = readl(&clk->gate_d01); in onenand_board_init()
30 value &= ~(1 << 2); /* CLK_ONENANDC */ in onenand_board_init()
31 value |= (1 << 2); in onenand_board_init()
32 writel(value, &clk->gate_d01); in onenand_board_init()
34 value = readl(&clk->src0); in onenand_board_init()
37 writel(value, &clk->src0); in onenand_board_init()
39 value = readl(&clk->div1); in onenand_board_init()
41 value |= (1 << 16); in onenand_board_init()
42 writel(value, &clk->div1); in onenand_board_init()
[all …]
/board/CZ.NIC/turris_omnia/
A Deeprom.c27 if (value[0] == '1' || value[0] == '2' || value[0] == '4') in eeprom_field_update_ramsz()
28 sz = value[0] - '0'; in eeprom_field_update_ramsz()
32 if (value[1] != '\0') in eeprom_field_update_ramsz()
47 if (strlen(value) != 2) { in eeprom_field_update_region()
52 memcpy(field->buf, value, 2); in eeprom_field_update_region()
72 char *value) in eeprom_field_update_ddr_speed() argument
74 if (value[0] == '\0') { in eeprom_field_update_ddr_speed()
110 if (value[0] == '\0') { in eeprom_field_update_bool()
117 if (value[1] != '\0') in eeprom_field_update_bool()
120 if (value[0] == '1' || value[0] == '0') in eeprom_field_update_bool()
[all …]
/board/nuvoton/poleg_evb/
A Dpoleg_evb.c50 char value[32]; in last_stage_init() local
54 sprintf(value, "%ldM", (gd->ram_size / 0x100000)); in last_stage_init()
55 env_set("mem", value); in last_stage_init()
62 sprintf(value, "uart8250,mmio32,0x%x", (u32)addr); in last_stage_init()
63 env_set("earlycon", value); in last_stage_init()
65 sprintf(value, "ttyS%d,115200n8", dev->seq_); in last_stage_init()
66 env_set("console", value); in last_stage_init()
/board/keymile/secu1/
A Dsocfpga.c28 int value; in secu1_is_fu2() local
36 value = gpio_get_value(GPIO_FU_DETECTION); in secu1_is_fu2()
38 if (value == 1) in secu1_is_fu2()
43 return value; in secu1_is_fu2()
/board/alliedtelesis/common/
A Dgpio_hog.h7 const char *gpio_name, int value);
10 const char *gpio_name, int value) in gpio_hog() argument
12 return gpio_hog_list(gpiod, 1, node_name, gpio_name, value); in gpio_hog()
A Dgpio_hog.c13 const char *node_name, const char *gpio_name, int value) in gpio_hog_list() argument
32 dm_gpio_set_value(&gpiod[i], value); in gpio_hog_list()
/board/kontron/sl-mx8mm/
A Dsl-mx8mm.c68 u32 value = readl(OCOTP_BASE_ADDR + 0x660); in fdt_set_usb_eth_addr() local
72 mac[0] = value >> 24; in fdt_set_usb_eth_addr()
73 mac[1] = value >> 16; in fdt_set_usb_eth_addr()
74 mac[2] = value >> 8; in fdt_set_usb_eth_addr()
75 mac[3] = value; in fdt_set_usb_eth_addr()
77 value = readl(OCOTP_BASE_ADDR + 0x650); in fdt_set_usb_eth_addr()
78 mac[4] = value >> 24; in fdt_set_usb_eth_addr()
79 mac[5] = value >> 16; in fdt_set_usb_eth_addr()
/board/freescale/ls1043ardb/
A Dcpld.h31 void cpld_write(unsigned int reg, u8 value);
32 void cpld_rev_bit(unsigned char *value);
35 #define CPLD_WRITE(reg, value) \ argument
36 cpld_write(offsetof(struct cpld_data, reg), value)
/board/motorola/mot/
A Dmot-spl.c34 int value; in gpio_early_init_uart() local
51 value = spl_gpio_get_value(NULL, TEGRA_GPIO(R, 0)); in gpio_early_init_uart()
54 if (!value) { in gpio_early_init_uart()
/board/freescale/ls1046ardb/
A Dcpld.h35 void cpld_write(unsigned int reg, u8 value);
36 void cpld_rev_bit(unsigned char *value);
40 #define CPLD_WRITE(reg, value) \ argument
41 cpld_write(offsetof(struct cpld_data, reg), value)
/board/phytec/pcm052/
A Dpcm052.c322 u32 value; in imx_get_mac_from_fuse() local
333 mac[0] = value >> 8; in imx_get_mac_from_fuse()
334 mac[1] = value; in imx_get_mac_from_fuse()
337 mac[2] = value >> 24; in imx_get_mac_from_fuse()
338 mac[3] = value >> 16; in imx_get_mac_from_fuse()
339 mac[4] = value >> 8; in imx_get_mac_from_fuse()
340 mac[5] = value; in imx_get_mac_from_fuse()
345 mac[0] = value >> 24; in imx_get_mac_from_fuse()
346 mac[1] = value >> 16; in imx_get_mac_from_fuse()
347 mac[2] = value >> 8; in imx_get_mac_from_fuse()
[all …]
/board/freescale/t208xqds/
A Dt208xqds.c258 u8 card_id, value; in esdhc_adapter_card_ident() local
264 value = QIXIS_READ(brdcfg[5]); in esdhc_adapter_card_ident()
265 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); in esdhc_adapter_card_ident()
266 QIXIS_WRITE(brdcfg[5], value); in esdhc_adapter_card_ident()
269 value = QIXIS_READ(pwr_ctl[1]); in esdhc_adapter_card_ident()
270 value |= QIXIS_EVDD_BY_SDHC_VS; in esdhc_adapter_card_ident()
271 QIXIS_WRITE(pwr_ctl[1], value); in esdhc_adapter_card_ident()
274 value = QIXIS_READ(brdcfg[5]); in esdhc_adapter_card_ident()
275 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); in esdhc_adapter_card_ident()
276 QIXIS_WRITE(brdcfg[5], value); in esdhc_adapter_card_ident()
/board/emulation/qemu-arm/
A Dqemu-arm.c191 void flash_write8(u8 value, void *addr) in flash_write8() argument
193 asm("strb %" __W "1, %0" : "=m"(*(u8 *)addr) : "r"(value)); in flash_write8()
196 void flash_write16(u16 value, void *addr) in flash_write16() argument
198 asm("strh %" __W "1, %0" : "=m"(*(u16 *)addr) : "r"(value)); in flash_write16()
201 void flash_write32(u32 value, void *addr) in flash_write32() argument
203 asm("str %" __W "1, %0" : "=m"(*(u32 *)addr) : "r"(value)); in flash_write32()
/board/ti/dra7xx/
A Devm.c381 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
388 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
389 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
400 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
417 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
437 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
448 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
465 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
495 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
506 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
[all …]
/board/htc/endeavoru/
A Dendeavoru-spl.c55 int value; in apx_hook() local
64 value = spl_gpio_get_value(NULL, TEGRA_GPIO(S, 0)); in apx_hook()
67 if (!value) { in apx_hook()
/board/freescale/t208xrdb/
A Dcpld.h28 void cpld_write(unsigned int reg, u8 value);
31 #define CPLD_WRITE(reg, value) \ argument
32 cpld_write(offsetof(struct cpld_data, reg), value)
/board/freescale/t104xrdb/
A Dcpld.h38 void cpld_write(unsigned int reg, u8 value);
41 #define CPLD_WRITE(reg, value)\ argument
42 cpld_write(offsetof(struct cpld_data, reg), value)
/board/freescale/t4rdb/
A Dcpld.h43 void cpld_write(unsigned int reg, u8 value);
46 #define CPLD_WRITE(reg, value) \ argument
47 cpld_write(offsetof(struct cpld_data, reg), value)
/board/freescale/t102xrdb/
A Dcpld.h29 void cpld_write(unsigned int reg, u8 value);
32 #define CPLD_WRITE(reg, value)\ argument
33 cpld_write(offsetof(struct cpld_data, reg), value)
/board/st/common/
A Dstpmic1.c188 u32 value; in stmpic_buck1_set() local
191 value = ((voltage_mv - 725) / 25) + 5; in stmpic_buck1_set()
192 if (value < 5) in stmpic_buck1_set()
193 value = 5; in stmpic_buck1_set()
194 if (value > 36) in stmpic_buck1_set()
195 value = 36; in stmpic_buck1_set()
200 STPMIC1_BUCK_VOUT(value)); in stmpic_buck1_set()
/board/BuR/zynq/env/
A Dbrcp150.env14 fdt get value cfgaddr_spi /binman/blob-ext@0 offset &&
15 fdt get value cfgsize_spi /binman/blob-ext@0 size
18 fdt get value fpgaaddr_spi /binman/blob-ext@1 offset &&
19 fdt get value fpgasize_spi /binman/blob-ext@1 size
22 fdt get value osaddr_spi /binman/blob-ext@2 offset &&
23 fdt get value ossize_spi /binman/blob-ext@2 size
26 fdt get value dtbaddr_spi /binman/blob-ext@3 offset &&
27 fdt get value dtbsize_spi /binman/blob-ext@3 size
30 fdt get value optaddr_spi /binman/blob-ext@5 offset &&
31 fdt get value optsize_spi /binman/blob-ext@5 size
A Dbrcp1.env14 fdt get value cfgaddr_spi /binman/blob-ext@0 offset &&
15 fdt get value cfgsize_spi /binman/blob-ext@0 size
18 fdt get value fpgaaddr_spi /binman/blob-ext@1 offset &&
19 fdt get value fpgasize_spi /binman/blob-ext@1 size
22 fdt get value osaddr_spi /binman/blob-ext@2 offset &&
23 fdt get value ossize_spi /binman/blob-ext@2 size
26 fdt get value dtbaddr_spi /binman/blob-ext@3 offset &&
27 fdt get value dtbsize_spi /binman/blob-ext@3 size
/board/freescale/p2041rdb/
A Dcpld.h51 void cpld_write(unsigned int reg, u8 value);
54 #define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value) argument
/board/freescale/common/
A Dqixis.h98 void qixis_write(unsigned int reg, u8 value);
105 void qixis_write_i2c(unsigned int reg, u8 value);
110 #define QIXIS_WRITE(reg, value) \ argument
111 qixis_write_i2c(offsetof(struct qixis, reg), value)
114 #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) argument
119 #define QIXIS_WRITE_I2C(reg, value) \ argument
120 qixis_write_i2c(offsetof(struct qixis, reg), value)

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