| /board/friendlyarm/nanopi2/ |
| A D | lcds.c | 93 .width = 800,
120 .width = 800,
147 .width = 800,
174 .width = 800,
201 .width = 800,
228 .width = 480,
360 .width = 640,
439 .width = 480,
465 .width = 480,
545 int width; member
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| A D | nxp-fb.h | 63 int width; member
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| A D | board.c | 138 sync->h_active_len = lcd->width; in nx_display_fixup_dp()
151 div = timing->h_sw + timing->h_bp + timing->h_fp + lcd->width; in nx_display_fixup_dp()
159 dp->top.screen_width = lcd->width; in nx_display_fixup_dp()
164 plane->width = lcd->width; in nx_display_fixup_dp()
177 if (lcd->width == 1920 && lcd->height == 1080) in nx_display_fixup_dp()
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| /board/samsung/common/ |
| A D | sromc.c | 30 int width; /* bus width in bytes */ in exyno5_sromc_probe() local
37 width = dev_read_s32_default(dev, "width", 2); in exyno5_sromc_probe()
40 if (width != 2) { in exyno5_sromc_probe()
41 log_debug("Unsupported bus width %d\n", width); in exyno5_sromc_probe()
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| /board/theadorable/ |
| A D | theadorable.c | 347 static int pcie_get_link_speed_width(pci_dev_t bdf, int *speed, int *width) in pcie_get_link_speed_width() argument
373 *width = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; in pcie_get_link_speed_width()
399 int width; in do_pcie_test() local
412 ret = pcie_get_link_speed_width(bdf, &speed, &width); in do_pcie_test()
420 printf("Established speed=%d width=%d\n", speed, width); in do_pcie_test()
421 if ((speed != 1 || width != 1)) { in do_pcie_test()
428 ret = pcie_get_link_speed_width(bdf, &speed, &width); in do_pcie_test()
436 printf("Established speed=%d width=%d\n", speed, width); in do_pcie_test()
437 if ((speed != 2 || width != 4)) { in do_pcie_test()
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| /board/gateworks/gw_ventana/ |
| A D | gw_ventana_spl.c | 156 .width = 16,
170 .width = 16,
184 .width = 16,
198 .width = 16,
494 .dsize = width/32, in spl_dram_init()
525 if (width == 16 && size_mb == 128) { in spl_dram_init()
532 } else if (width == 16 && size_mb == 256) { in spl_dram_init()
540 } else if (width == 16 && size_mb == 512) { in spl_dram_init()
552 } else if (width == 32 && size_mb == 256) { in spl_dram_init()
560 } else if (width == 32 && size_mb == 512) { in spl_dram_init()
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| /board/ge/b1x5v2/ |
| A D | spl.c | 258 .width = 16,
271 .width = 16,
284 .width = 16,
294 static void spl_dram_init(u8 width, u32 memsize) { in spl_dram_init() argument
297 .dsize = width / 32, in spl_dram_init()
315 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); in spl_dram_init()
327 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); in spl_dram_init()
338 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); in spl_dram_init()
453 u8 width; in memory_init() local
468 width = is_cpu_type(MXC_CPU_MX6SOLO) ? 32 : 64; in memory_init()
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| /board/boundary/nitrogen6x/ |
| A D | ddr-setup.cfg | 19 * memory bus width: 64 bits x16/x32/x64
21 * memory bus width: 64 bits x16/x32/x64
23 * memory bus width: 32 bits x16/x32
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| /board/freescale/mx6memcal/ |
| A D | spl.c | 250 .width = 16,
264 .width = 16,
278 .width = 16,
292 .width = 16,
306 .width = 32,
320 .width = 32,
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| /board/bluewater/gurnard/ |
| A D | gurnard.c | 119 static void lcd_splash(int width, int height) in lcd_splash() argument
125 memset(base_addr, 0xff, width * height * 2); in lcd_splash()
134 posx = x + (width - BMP_LOGO_WIDTH) / 2; in lcd_splash()
136 base_addr[posy * width + posx] = colour; in lcd_splash()
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| /board/technexion/pico-imx6ul/ |
| A D | spl.c | 88 .width = 16,
117 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); in imx6ul_spl_dram_cfg_size()
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| /board/phytec/pcl063/ |
| A D | spl.c | 76 .width = 16,
101 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); in spl_dram_init()
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| /board/myir/mys_6ulx/ |
| A D | spl.c | 75 .width = 16,
100 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); in spl_dram_init()
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| /board/seeed/npi_imx6ull/ |
| A D | spl.c | 74 .width = 16,
99 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); in spl_dram_init()
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| /board/variscite/dart_6ul/ |
| A D | spl.c | 82 .width = 16,
110 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); in spl_dram_init()
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| /board/solidrun/mx6cuboxi/ |
| A D | mx6cuboxi.c | 728 .width = 16,
741 .width = 16,
764 static void spl_dram_init(int width) in spl_dram_init() argument
768 .dsize = width / 32, in spl_dram_init()
787 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); in spl_dram_init()
789 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); in spl_dram_init()
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| /board/freescale/mx6ul_14x14_evk/ |
| A D | mx6ul_14x14_evk.c | 344 .width = 16,
415 .width = 16,
442 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); in spl_dram_init()
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| /board/engicam/common/ |
| A D | spl.c | 194 .width = 16,
340 .width = 16,
392 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); in spl_dram_init()
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| /board/skyworth/hc2910-2aghd05/ |
| A D | README | 9 DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
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| /board/technexion/pico-imx6/ |
| A D | spl.c | 144 .width = 16,
158 .width = 16,
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| /board/udoo/neo/ |
| A D | neo.c | 307 .width = 16,
321 .width = 16,
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| /board/kontron/sl-mx6ul/ |
| A D | spl.c | 174 .width = 16,
195 .width = 16,
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| /board/softing/vining_2000/ |
| A D | vining_2000.c | 503 .width = 32,
529 .dsize = mem_ddr.width / 32, in vining2000_spl_dram_init()
546 mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); in vining2000_spl_dram_init()
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| /board/bticino/mamoj/ |
| A D | spl.c | 95 .width = 32,
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| /board/freescale/mx6slevk/ |
| A D | mx6slevk.c | 317 .width = 32,
345 .dsize = mem_ddr.width / 32, in spl_dram_init()
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