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Searched refs:CACHE_LINE_SIZE (Results 1 – 2 of 2) sorted by relevance

/drivers/ddr/marvell/axp/
A Dddr3_sdram.c573 flush_l1_v7(line + CACHE_LINE_SIZE); in ddr3_flush_l1_line()
577 flush_l1_v6(line + CACHE_LINE_SIZE); in ddr3_flush_l1_line()
A Dddr3_hw_training.h89 #define CACHE_LINE_SIZE 0x20 macro

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