CACHE_LINE_SIZE (reference) in projects: drivers

Searched refs:CACHE_LINE_SIZE (Results 1 – 2 of 2) sorted by relevance

/drivers/ddr/marvell/axp/
A D	ddr3_sdram.c	`573 flush_l1_v7(line + CACHE_LINE_SIZE); in ddr3_flush_l1_line() 577 flush_l1_v6(line + CACHE_LINE_SIZE); in ddr3_flush_l1_line()`
A D	ddr3_hw_training.h	`89 #define CACHE_LINE_SIZE 0x20 macro`

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