| /drivers/clk/qcom/ |
| A D | clock-sdm845.c | 29 F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
33 F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
34 F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
35 F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
36 F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
37 F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
38 F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
40 F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
42 F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
51 F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
[all …]
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| A D | clock-sm8150.c | 44 F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
45 F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
46 F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
47 F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
48 F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
49 F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
62 F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
63 F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
70 F(33333333, CFG_CLK_SRC_GPLL0_EVEN, 9, 0, 0),
80 F(20000000, CFG_CLK_SRC_GPLL0_EVEN, 15, 0, 0),
[all …]
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| A D | clock-sm8550.c | 31 F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
32 F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
33 F(51200000, CFG_CLK_SRC_GPLL0_EVEN, 1, 64, 375),
34 F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
35 F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
36 F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
37 F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
44 F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
45 F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
46 F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
[all …]
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| A D | clock-sm8250.c | 30 F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
31 F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
34 F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
35 F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
36 F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
37 F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
38 F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
39 F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
40 F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
48 F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
[all …]
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| A D | clock-sm8650.c | 27 F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
31 F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
32 F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
33 F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
34 F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
35 F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
36 F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
43 F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
44 F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
50 F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
[all …]
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| A D | clock-x1e80100.c | 27 F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
31 F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
32 F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
33 F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
34 F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
35 F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
36 F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
43 F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
44 F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
50 F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
[all …]
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| A D | clock-sc7280.c | 28 F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
36 F(60000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 0, 0),
37 F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
73 clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN); in sc7280_set_rate()
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| A D | clock-qcom.h | 22 #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) macro
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