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Searched refs:CLK_CTRL_DIV0_SHIFT (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/
A Dclk_zynq.c34 #define CLK_CTRL_DIV0_SHIFT 8 macro
35 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
178 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_cpu_rate()
233 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_dci_rate()
250 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_peripheral_rate()
341 clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT; in zynq_clk_set_peripheral_rate()
A Dclk_zynqmp.c98 #define CLK_CTRL_DIV0_SHIFT 8 macro
99 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
437 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_cpu_rate()
461 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_ddr_rate()
509 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_peripheral_rate()
549 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_crf_crl_rate()
597 div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_crf_crl_rate()
676 clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_set_peripheral_rate()
678 mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) | in zynqmp_clk_set_peripheral_rate()

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