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Searched refs:CPS_REG_READ (Results 1 – 4 of 4) sorted by relevance

/drivers/ram/k3-ddrss/
A Dlpddr4.c107 regval = CPS_FLD_SET(LPDDR4__START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG))); in lpddr4_startsequencecontroller()
178 *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset)); in lpddr4_readreg()
183 *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset)); in lpddr4_readreg()
189 *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset)); in lpddr4_readreg()
483 phyindepirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG)); in lpddr4_checkphyindepinterrupt()
515 regval = CPS_REG_READ(regaddress); in lpddr4_checkcatrainingerror()
534 regval = CPS_REG_READ(regaddress); in lpddr4_checkgatelvlerror()
553 regval = CPS_REG_READ(regaddress); in lpddr4_checkreadlvlerror()
572 regval = CPS_REG_READ(regaddress); in lpddr4_checkdqtrainingerror()
608 regval = CPS_REG_READ(reg); in lpddr4_seterror()
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A Dlpddr4_am6x.c86 …regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_E… in lpddr4_enablepiinitiator()
131 *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MODE__REG)); in lpddr4_checkctlinterrupt_4()
155 *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TIMEOUT__REG)); in lpddr4_checkctlinterrupt_2()
157 *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TRAINING__REG)); in lpddr4_checkctlinterrupt_2()
159 *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_USERIF__REG)); in lpddr4_checkctlinterrupt_2()
178 …ctlmasterirqstatus = (CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MASTER__REG)) & (~((u32)1 << 3… in lpddr4_checkctlinterrupt()
204 …regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_BIST_… in lpddr4_ackctlinterrupt_4()
279 regval = CPS_REG_READ(regaddress); in lpddr4_checkwrlvlerror()
349 lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA__REG)); in lpddr4_checkmmrreaderror()
351 lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG)); in lpddr4_checkmmrreaderror()
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A Dlpddr4_j721e.c26 …regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_E… in lpddr4_enablepiinitiator()
41 …*mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1_… in lpddr4_getctlinterruptmask()
85 ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_1__REG)); in lpddr4_checkctlinterrupt()
88 ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_0__REG)); in lpddr4_checkctlinterrupt()
135 regval = CPS_REG_READ(regaddress); in lpddr4_checkwrlvlerror()
155 regval = CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD, CPS_REG_READ(regaddress)); in lpddr4_setrxoffseterror()
194 …fldval = CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)… in lpddr4_geteccenable()
235 if (CPS_FLD_READ(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U) in lpddr4_getreducmode()
250 …regval = (u32)CPS_FLD_WRITE(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG)), *… in lpddr4_setreducmode()
268 lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG)); in lpddr4_checkmmrreaderror()
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A Dcps_drv_lpddr4.h18 #define CPS_REG_READ(reg) (cps_regread((volatile u32 *)(reg))) macro

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