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Searched refs:CPS_REG_WRITE (Results 1 – 4 of 4) sorted by relevance

/drivers/ram/k3-ddrss/
A Dlpddr4.c105 CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval); in lpddr4_startsequencecontroller()
108 CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval); in lpddr4_startsequencecontroller()
300 CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval); in lpddr4_getmmrregister()
469 CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval); in lpddr4_setphyindepinterruptmask()
499 CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval); in lpddr4_ackphyindepinterrupt()
645 CPS_REG_WRITE(regaddress, regval); in lpddr4_setphysnapsettings()
661 CPS_REG_WRITE(regaddress, regval); in lpddr4_setphyadrsnapsettings()
969 CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval); in lpddr4_setdbimode()
1007 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG), regval); in lpddr4_updatefsp2refrateparams()
1018 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG), regval); in lpddr4_updatefsp1refrateparams()
[all …]
A Dlpddr4_am6x.c85 CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)), regval); in lpddr4_enablepiinitiator()
87 CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval); in lpddr4_enablepiinitiator()
120 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG), regval); in lpddr4_setctlinterruptmask()
202 …CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MODE__REG), (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[int… in lpddr4_ackctlinterrupt_4()
206 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG), regval); in lpddr4_ackctlinterrupt_4()
210 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG), regval); in lpddr4_ackctlinterrupt_4()
222 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG), regval); in lpddr4_ackctlinterrupt_3()
226 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG), regval); in lpddr4_ackctlinterrupt_3()
241 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG), regval); in lpddr4_ackctlinterrupt_2()
261 …CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MISC__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[in… in lpddr4_ackctlinterrupt()
[all …]
A Dlpddr4_j721e.c28 CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval); in lpddr4_enablepiinitiator()
65 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval); in lpddr4_setctlinterruptmask()
69 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval); in lpddr4_setctlinterruptmask()
115 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG), regval); in lpddr4_ackctlinterrupt()
118 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG), regval); in lpddr4_ackctlinterrupt()
223 CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval); in lpddr4_seteccenable()
251 CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval); in lpddr4_setreducmode()
A Dcps_drv_lpddr4.h20 #define CPS_REG_WRITE(reg, value) (cps_regwrite((volatile u32 *)(reg), (u32)(value))) macro

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