Searched refs:CRX_PHY_REG (Results 1 – 9 of 9) sorted by relevance
| /drivers/ddr/marvell/a38x/ |
| A D | ddr3_training_bist.c | 508 ddr3_tip_read_adll_value(0, rd_ctrl_adll, CRX_PHY_REG(cs), MASK_ALL_BITS); in mv_ddr_dm_vw_get()
610 subphy, DDR_PHY_DATA, CRX_PHY_REG(cs), in mv_ddr_dm_vw_get()
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| A D | mv_ddr_regs.h | 470 #define CRX_PHY_REG(cs) (CRX_PHY_BASE + (cs) * 0x4) macro
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| A D | ddr3_training_ip_engine.c | 616 reg_data = CRX_PHY_REG(effective_cs); in ddr3_tip_ip_training()
1635 CRX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
1657 CRX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
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| A D | ddr3_training_pbs.c | 73 CRX_PHY_REG(effective_cs) : in ddr3_tip_pbs()
854 CRX_PHY_REG(effective_cs) : in ddr3_tip_pbs()
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| A D | ddr3_debug.c | 737 CRX_PHY_REG(csindex), in ddr3_tip_print_stability_log()
1102 reg = (direction == 0) ? CTX_PHY_REG(cs) : CRX_PHY_REG(cs); in ddr3_tip_run_sweep_test()
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| A D | ddr3_training_centralization.c | 103 reg_phy_off = CRX_PHY_REG(effective_cs); in ddr3_tip_centralization()
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| A D | ddr3_training_leveling.c | 427 CRX_PHY_REG(0), in ddr3_tip_dynamic_per_bit_read_leveling()
663 CRX_PHY_REG(0), in ddr3_tip_dynamic_per_bit_read_leveling()
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| A D | mv_ddr4_training_calibration.c | 1891 CRX_PHY_REG(effective_cs), in mv_ddr4_receiver_calibration()
2000 CRX_PHY_REG(effective_cs), in mv_ddr4_receiver_calibration()
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| A D | ddr3_training.c | 2020 CRX_PHY_REG(effective_cs), phy_reg3_val)); in ddr3_tip_ddr3_reset_phy_regs()
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