Searched refs:CTX_PHY_REG (Results 1 – 10 of 10) sorted by relevance
| /drivers/ddr/marvell/a38x/ |
| A D | ddr3_debug.c | 731 CTX_PHY_REG(csindex), in ddr3_tip_print_stability_log()
1102 reg = (direction == 0) ? CTX_PHY_REG(cs) : CRX_PHY_REG(cs); in ddr3_tip_run_sweep_test()
1267 CTX_PHY_REG(cs), MASK_ALL_BITS); in ddr3_tip_run_leveling_sweep_test()
1311 CTX_PHY_REG(cs), in ddr3_tip_run_leveling_sweep_test()
1362 CTX_PHY_REG(cs), in ddr3_tip_run_leveling_sweep_test()
1400 ddr3_tip_write_adll_value(dev_num, ctrl_adll1, CTX_PHY_REG(cs)); in ddr3_tip_run_leveling_sweep_test()
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| A D | ddr3_training_bist.c | 507 ddr3_tip_read_adll_value(0, wr_ctrl_adll, CTX_PHY_REG(cs), MASK_ALL_BITS); in mv_ddr_dm_vw_get()
558 DDR_PHY_DATA, CTX_PHY_REG(cs), adll_tap); in mv_ddr_dm_vw_get()
588 subphy, DDR_PHY_DATA, CTX_PHY_REG(cs), in mv_ddr_dm_vw_get()
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| A D | ddr3_training_leveling.c | 1190 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1210 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1215 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1236 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1241 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
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| A D | mv_ddr_regs.h | 460 #define CTX_PHY_REG(cs) (CTX_PHY_BASE + (cs) * 0x4) macro
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| A D | mv_ddr4_training_leveling.c | 192 CTX_PHY_REG(0), &wl_invert); in mv_ddr4_xsb_comp_test()
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| A D | ddr3_training_ip_engine.c | 612 reg_data = CTX_PHY_REG(effective_cs); in ddr3_tip_ip_training()
1621 CTX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
1643 CTX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
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| A D | ddr3_training_pbs.c | 74 CTX_PHY_REG(effective_cs); in ddr3_tip_pbs()
855 CTX_PHY_REG(effective_cs); in ddr3_tip_pbs()
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| A D | mv_ddr4_training_calibration.c | 314 CTX_PHY_REG(effective_cs), in mv_ddr4_dq_vref_calibration()
2073 CTX_PHY_REG(cs), ®_val); in mv_ddr4_dm_tuning()
2102 CTX_PHY_REG(cs), ctx_vector[subphy]); in mv_ddr4_dm_tuning()
2303 CTX_PHY_REG(cs), ctx_vector[subphy]); in mv_ddr4_dm_tuning()
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| A D | ddr3_training_centralization.c | 99 reg_phy_off = CTX_PHY_REG(effective_cs); in ddr3_tip_centralization()
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| A D | ddr3_training.c | 2024 CTX_PHY_REG(effective_cs), phy_reg1_val)); in ddr3_tip_ddr3_reset_phy_regs()
2110 CTX_PHY_REG(effective_cs), reg_val1)); in ddr3_tip_adll_regs_bypass()
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