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Searched refs:DENALI_CTL_23 (Results 1 – 7 of 7) sorted by relevance

/drivers/ddr/imx/imx8ulp/
A Dddr_init.c29 #define DENALI_CTL_23 (DDR_CTL_BASE_ADDR + 4 * 23) macro
59 reg_val = readl(DENALI_CTL_23) & ~(0x3 << 24); in ddr_enable_pll_bypass()
60 writel(reg_val, DENALI_CTL_23); in ddr_enable_pll_bypass()
/drivers/ram/k3-ddrss/am64/
A Dlpddr4_ctl_regs.h45 volatile u32 DENALI_CTL_23; member
A Dlpddr4_ddr_controller_macros.h365 #define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
/drivers/ram/k3-ddrss/j721e/
A Dlpddr4_ctl_regs.h45 volatile u32 DENALI_CTL_23; member
A Dlpddr4_ddr_controller_macros.h361 #define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
/drivers/ram/k3-ddrss/am62a/
A Dlpddr4_ctl_regs.h47 volatile u32 DENALI_CTL_23; member
A Dlpddr4_ddr_controller_macros.h365 #define LPDDR4__TRST_PWRON__REG DENALI_CTL_23

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