Searched refs:DENALI_CTL_25 (Results 1 – 7 of 7) sorted by relevance
30 #define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25) macro76 writel(reg_val, DENALI_CTL_25); in ddr_enable_pll_bypass()
47 volatile u32 DENALI_CTL_25; member
381 #define LPDDR4__TDLL_F0__REG DENALI_CTL_25387 #define LPDDR4__TDLL_F1__REG DENALI_CTL_25
379 #define LPDDR4__MC_RESERVED0__REG DENALI_CTL_25385 #define LPDDR4__MC_RESERVED1__REG DENALI_CTL_25
49 volatile u32 DENALI_CTL_25; member
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