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Searched refs:DENALI_CTL_25 (Results 1 – 7 of 7) sorted by relevance

/drivers/ddr/imx/imx8ulp/
A Dddr_init.c30 #define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25) macro
76 writel(reg_val, DENALI_CTL_25); in ddr_enable_pll_bypass()
/drivers/ram/k3-ddrss/am64/
A Dlpddr4_ctl_regs.h47 volatile u32 DENALI_CTL_25; member
A Dlpddr4_ddr_controller_macros.h381 #define LPDDR4__TDLL_F0__REG DENALI_CTL_25
387 #define LPDDR4__TDLL_F1__REG DENALI_CTL_25
/drivers/ram/k3-ddrss/j721e/
A Dlpddr4_ctl_regs.h47 volatile u32 DENALI_CTL_25; member
A Dlpddr4_ddr_controller_macros.h379 #define LPDDR4__MC_RESERVED0__REG DENALI_CTL_25
385 #define LPDDR4__MC_RESERVED1__REG DENALI_CTL_25
/drivers/ram/k3-ddrss/am62a/
A Dlpddr4_ctl_regs.h49 volatile u32 DENALI_CTL_25; member
A Dlpddr4_ddr_controller_macros.h381 #define LPDDR4__TDLL_F0__REG DENALI_CTL_25
387 #define LPDDR4__TDLL_F1__REG DENALI_CTL_25

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