Home
last modified time | relevance | path

Searched refs:DENALI_PHY_1547 (Results 1 – 3 of 3) sorted by relevance

/drivers/ddr/imx/imx8ulp/
A Dddr_init.c38 #define DENALI_PHY_1547 (DDR_PHY_BASE_ADDR + 4 * 1547) macro
63 reg_val = readl(DENALI_PHY_1547) & ~(0x1 << 8); in ddr_enable_pll_bypass()
64 writel(reg_val, DENALI_PHY_1547); in ddr_enable_pll_bypass()
/drivers/ram/k3-ddrss/am62a/
A Dlpddr4_address_slice_2_macros.h207 #define LPDDR4__PHY_ADR_CALVL_START_2__REG DENALI_PHY_1547
213 #define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__REG DENALI_PHY_1547
A Dlpddr4_ctl_regs.h1548 volatile u32 DENALI_PHY_1547; member

Completed in 21 milliseconds