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Searched refs:DENALI_PHY_1555 (Results 1 – 3 of 3) sorted by relevance

/drivers/ddr/imx/imx8ulp/
A Dddr_init.c39 #define DENALI_PHY_1555 (DDR_PHY_BASE_ADDR + 4 * 1555) macro
71 reg_val = readl(DENALI_PHY_1555) | 0x1; in ddr_enable_pll_bypass()
72 writel(reg_val, DENALI_PHY_1555); in ddr_enable_pll_bypass()
/drivers/ram/k3-ddrss/am62a/
A Dlpddr4_address_slice_2_macros.h319 #define LPDDR4__PHY_ADR_CALVL_OBS1_2__REG DENALI_PHY_1555
A Dlpddr4_ctl_regs.h1556 volatile u32 DENALI_PHY_1555; member

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