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Searched refs:DRAM_ZQ_TIMING_REG (Results 1 – 3 of 3) sorted by relevance

/drivers/ddr/marvell/a38x/
A Dmv_ddr4_training.c78 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DRAM_ZQ_TIMING_REG, in mv_ddr4_sdram_config()
84 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DRAM_ZQ_TIMING_REG, in mv_ddr4_sdram_config()
A Dmv_ddr_regs.h218 #define DRAM_ZQ_TIMING_REG 0x14e8 macro
/drivers/ddr/marvell/a38x/old/
A Dddr3_training_ip_flow.h124 #define DRAM_ZQ_TIMING_REG 0x14e8 macro

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