Searched refs:DUAL_DUNIT_CFG_REG (Results 1 – 8 of 8) sorted by relevance
| /drivers/ddr/marvell/a38x/ |
| A D | ddr3_training_centralization.c | 90 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_centralization()
94 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_centralization()
515 if_id, DUAL_DUNIT_CFG_REG, in ddr3_tip_centralization()
553 if_id, DUAL_DUNIT_CFG_REG, in ddr3_tip_special_rx()
558 if_id, DUAL_DUNIT_CFG_REG, in ddr3_tip_special_rx()
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| A D | ddr3_training_leveling.c | 66 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, in ddr3_tip_dynamic_read_leveling()
71 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_read_leveling()
295 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_read_leveling()
440 DUAL_DUNIT_CFG_REG, &cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
445 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_per_bit_read_leveling()
747 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
841 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_dynamic_write_leveling()
848 DUAL_DUNIT_CFG_REG, 0, (1 << 3))); in ddr3_tip_dynamic_write_leveling()
1141 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_write_leveling()
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| A D | ddr3_training_pbs.c | 64 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_pbs()
69 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_pbs()
871 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_pbs()
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| A D | ddr3_training_ip_engine.c | 517 DUAL_DUNIT_CFG_REG, 1 << 3, 1 << 3)); in ddr3_tip_ip_training()
526 DUAL_DUNIT_CFG_REG, 0, 1 << 3)); in ddr3_tip_ip_training()
859 (dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG, in ddr3_tip_read_training_result()
1007 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_load_all_pattern_to_mem()
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| A D | mv_ddr_regs.h | 343 #define DUAL_DUNIT_CFG_REG 0x16d8 macro
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| A D | mv_ddr4_training_calibration.c | 365 status = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG, in mv_ddr4_centralization()
371 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG, in mv_ddr4_centralization()
664 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG, in mv_ddr4_centralization()
1167 ddr3_tip_if_read(dev, ACCESS_TYPE_UNICAST, iface, DUAL_DUNIT_CFG_REG, in mv_ddr4_tap_tuning()
1171 ddr3_tip_if_write(dev, ACCESS_TYPE_UNICAST, iface, DUAL_DUNIT_CFG_REG, in mv_ddr4_tap_tuning()
1498 ddr3_tip_if_write(dev, ACCESS_TYPE_UNICAST, iface, DUAL_DUNIT_CFG_REG, in mv_ddr4_tap_tuning()
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| A D | mv_ddr_plat.c | 448 reg = reg_read(DUAL_DUNIT_CFG_REG); in ddr3_tip_a38x_select_ddr_controller()
455 reg_write(DUAL_DUNIT_CFG_REG, reg); in ddr3_tip_a38x_select_ddr_controller()
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| A D | ddr3_training.c | 406 if_id, DUAL_DUNIT_CFG_REG, 0, in hws_ddr3_tip_init_controller()
1330 DUAL_DUNIT_CFG_REG, 0, 0x8)); in ddr3_tip_freq_set()
1631 DUAL_DUNIT_CFG_REG, in ddr3_tip_freq_set()
2705 if_id, DUAL_DUNIT_CFG_REG, 1 << 3, in ddr3_tip_enable_init_sequence()
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Completed in 31 milliseconds