1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2021 Nuvoton Technology Corp.
4 */
5
6 #include <cpu_func.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <miiphy.h>
10 #include <malloc.h>
11 #include <net.h>
12 #include <regmap.h>
13 #include <serial.h>
14 #include <syscon.h>
15 #include <asm/io.h>
16 #include <linux/err.h>
17 #include <linux/iopoll.h>
18
19 #define MAC_ADDR_SIZE 6
20 #define CFG_TX_DESCR_NUM 32
21 #define CFG_RX_DESCR_NUM 32
22
23 #define TX_TOTAL_BUFSIZE \
24 ((CFG_TX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
25 #define RX_TOTAL_BUFSIZE \
26 ((CFG_RX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
27
28 #define CFG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
29
30 struct npcm750_rxbd {
31 unsigned int sl;
32 unsigned int buffer;
33 unsigned int reserved;
34 unsigned int next;
35 } __aligned(ARCH_DMA_MINALIGN);
36
37 struct npcm750_txbd {
38 unsigned int mode;
39 unsigned int buffer;
40 unsigned int sl;
41 unsigned int next;
42 } __aligned(ARCH_DMA_MINALIGN);
43
44 struct emc_regs {
45 u32 camcmr; /* 0x00 */
46 u32 camen; /* 0x04 */
47 u32 cam0m; /* 0x08 */
48 u32 cam0l; /* 0x0c */
49 u32 cam1m; /* 0x10 */
50 u32 cam1l; /* 0x14 */
51 u32 cam2m; /* 0x18 */
52 u32 cam2l; /* 0x1c */
53 u32 cam3m; /* 0x20 */
54 u32 cam3l; /* 0x24 */
55 u32 cam4m; /* 0x28 */
56 u32 cam4l; /* 0x2c */
57 u32 cam5m; /* 0x30 */
58 u32 cam5l; /* 0x34 */
59 u32 cam6m; /* 0x38 */
60 u32 cam6l; /* 0x3c */
61 u32 cam7m; /* 0x40 */
62 u32 cam7l; /* 0x44 */
63 u32 cam8m; /* 0x48 */
64 u32 cam8l; /* 0x4c */
65 u32 cam9m; /* 0x50 */
66 u32 cam9l; /* 0x54 */
67 u32 cam10m; /* 0x58 */
68 u32 cam10l; /* 0x5c */
69 u32 cam11m; /* 0x60 */
70 u32 cam11l; /* 0x64 */
71 u32 cam12m; /* 0x68 */
72 u32 cam12l; /* 0x6c */
73 u32 cam13m; /* 0x70 */
74 u32 cam13l; /* 0x74 */
75 u32 cam14m; /* 0x78 */
76 u32 cam14l; /* 0x7c */
77 u32 cam15m; /* 0x80 */
78 u32 cam15l; /* 0x84 */
79 u32 txdlsa; /* 0x88 */
80 u32 rxdlsa; /* 0x8c */
81 u32 mcmdr; /* 0x90 */
82 u32 miid; /* 0x94 */
83 u32 miida; /* 0x98 */
84 u32 fftcr; /* 0x9c */
85 u32 tsdr; /* 0xa0 */
86 u32 rsdr; /* 0xa4 */
87 u32 dmarfc; /* 0xa8 */
88 u32 mien; /* 0xac */
89 u32 mista; /* 0xb0 */
90 u32 mgsta; /* 0xb4 */
91 u32 mpcnt; /* 0xb8 */
92 u32 mrpc; /* 0xbc */
93 u32 mrpcc; /* 0xc0 */
94 u32 mrepc; /* 0xc4 */
95 u32 dmarfs; /* 0xc8 */
96 u32 ctxdsa; /* 0xcc */
97 u32 ctxbsa; /* 0xd0 */
98 u32 crxdsa; /* 0xd4 */
99 u32 crxbsa; /* 0xd8 */
100 };
101
102 struct npcm750_eth_dev {
103 struct npcm750_txbd tdesc[CFG_TX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
104 struct npcm750_rxbd rdesc[CFG_RX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
105 u8 txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
106 u8 rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
107 struct emc_regs *emc_regs_p;
108 struct phy_device *phydev;
109 struct mii_dev *bus;
110 struct npcm750_txbd *curr_txd;
111 struct npcm750_rxbd *curr_rxd;
112 u32 interface;
113 u32 max_speed;
114 u32 idx;
115 struct regmap *gcr_regmap;
116 };
117
118 struct npcm750_eth_pdata {
119 struct eth_pdata eth_pdata;
120 };
121
122 /* mac controller bit */
123 #define MCMDR_RXON BIT(0)
124 #define MCMDR_ACP BIT(3)
125 #define MCMDR_SPCRC BIT(5)
126 #define MCMDR_TXON BIT(8)
127 #define MCMDR_NDEF BIT(9)
128 #define MCMDR_FDUP BIT(18)
129 #define MCMDR_ENMDC BIT(19)
130 #define MCMDR_OPMOD BIT(20)
131 #define MCMDR_SWR BIT(24)
132
133 /* cam command regiser */
134 #define CAMCMR_AUP 0x01
135 #define CAMCMR_AMP BIT(1)
136 #define CAMCMR_ABP BIT(2)
137 #define CAMCMR_CCAM BIT(3)
138 #define CAMCMR_ECMP BIT(4)
139 #define CAM0EN 0x01
140
141 /* mac mii controller bit */
142 #define MDCON BIT(19)
143 #define PHYAD BIT(8)
144 #define PHYWR BIT(16)
145 #define PHYBUSY BIT(17)
146 #define PHYPRESP BIT(18)
147 #define CAM_ENTRY_SIZE 0x08
148
149 /* rx and tx status */
150 #define TXDS_TXCP BIT(19)
151 #define RXDS_CRCE BIT(17)
152 #define RXDS_PTLE BIT(19)
153 #define RXDS_RXGD BIT(20)
154 #define RXDS_ALIE BIT(21)
155 #define RXDS_RP BIT(22)
156
157 /* mac interrupt status*/
158 #define MISTA_RXINTR BIT(0)
159 #define MISTA_CRCE BIT(1)
160 #define MISTA_RXOV BIT(2)
161 #define MISTA_PTLE BIT(3)
162 #define MISTA_RXGD BIT(4)
163 #define MISTA_ALIE BIT(5)
164 #define MISTA_RP BIT(6)
165 #define MISTA_MMP BIT(7)
166 #define MISTA_DFOI BIT(8)
167 #define MISTA_DENI BIT(9)
168 #define MISTA_RDU BIT(10)
169 #define MISTA_RXBERR BIT(11)
170 #define MISTA_CFR BIT(14)
171 #define MISTA_TXINTR BIT(16)
172 #define MISTA_TXEMP BIT(17)
173 #define MISTA_TXCP BIT(18)
174 #define MISTA_EXDEF BIT(19)
175 #define MISTA_NCS BIT(20)
176 #define MISTA_TXABT BIT(21)
177 #define MISTA_LC BIT(22)
178 #define MISTA_TDU BIT(23)
179 #define MISTA_TXBERR BIT(24)
180
181 #define ENSTART 0x01
182 #define ENRXINTR BIT(0)
183 #define ENCRCE BIT(1)
184 #define EMRXOV BIT(2)
185 #define ENPTLE BIT(3)
186 #define ENRXGD BIT(4)
187 #define ENALIE BIT(5)
188 #define ENRP BIT(6)
189 #define ENMMP BIT(7)
190 #define ENDFO BIT(8)
191 #define ENDENI BIT(9)
192 #define ENRDU BIT(10)
193 #define ENRXBERR BIT(11)
194 #define ENCFR BIT(14)
195 #define ENTXINTR BIT(16)
196 #define ENTXEMP BIT(17)
197 #define ENTXCP BIT(18)
198 #define ENTXDEF BIT(19)
199 #define ENNCS BIT(20)
200 #define ENTXABT BIT(21)
201 #define ENLC BIT(22)
202 #define ENTDU BIT(23)
203 #define ENTXBERR BIT(24)
204
205 #define RX_STAT_RBC 0xffff
206 #define RX_STAT_RXINTR BIT(16)
207 #define RX_STAT_CRCE BIT(17)
208 #define RX_STAT_PTLE BIT(19)
209 #define RX_STAT_RXGD BIT(20)
210 #define RX_STAT_ALIE BIT(21)
211 #define RX_STAT_RP BIT(22)
212 #define RX_STAT_OWNER (BIT(30) | BIT(31))
213
214 #define TX_STAT_TBC 0xffff
215 #define TX_STAT_TXINTR BIT(16)
216 #define TX_STAT_DEF BIT(17)
217 #define TX_STAT_TXCP BIT(19)
218 #define TX_STAT_EXDEF BIT(20)
219 #define TX_STAT_NCS BIT(21)
220 #define TX_STAT_TXBT BIT(22)
221 #define TX_STAT_LC BIT(23)
222 #define TX_STAT_TXHA BIT(24)
223 #define TX_STAT_PAU BIT(25)
224 #define TX_STAT_SQE BIT(26)
225
226 /* rx and tx owner bit */
227 #define RX_OWEN_DMA BIT(31)
228 #define RX_OWEN_CPU 0x00 //bit 30 & bit 31
229 #define TX_OWEN_DMA BIT(31)
230 #define TX_OWEN_CPU (~(BIT(31)))
231
232 /* tx frame desc controller bit */
233 #define MACTXINTEN 0x04
234 #define CRCMODE 0x02
235 #define PADDINGMODE 0x01
236
237 /* fftcr controller bit */
238 #define RXTHD 0x03
239 #define TXTHD (BIT(8) | BIT(9))
240 #define BLENGTH BIT(21)
241
242 /* global setting for driver */
243 #define RX_DESC_SIZE 128
244 #define TX_DESC_SIZE 64
245 #define MAX_RBUFF_SZ 0x600
246 #define MAX_TBUFF_SZ 0x600
247 #define TX_TIMEOUT 50
248 #define DELAY 1000
249 #define CAM0 0x0
250 #define RX_POLL_SIZE (RX_DESC_SIZE / 2)
251 #define MII_TIMEOUT 100
252 #define GCR_INTCR 0x3c
253 #define INTCR_R1EN BIT(5)
254
255 enum MIIDA_MDCCR_T {
256 MIIDA_MDCCR_4 = 0x00,
257 MIIDA_MDCCR_6 = 0x01,
258 MIIDA_MDCCR_8 = 0x02,
259 MIIDA_MDCCR_12 = 0x03,
260 MIIDA_MDCCR_16 = 0x04,
261 MIIDA_MDCCR_20 = 0x05,
262 MIIDA_MDCCR_24 = 0x06,
263 MIIDA_MDCCR_28 = 0x07,
264 MIIDA_MDCCR_30 = 0x08,
265 MIIDA_MDCCR_32 = 0x09,
266 MIIDA_MDCCR_36 = 0x0A,
267 MIIDA_MDCCR_40 = 0x0B,
268 MIIDA_MDCCR_44 = 0x0C,
269 MIIDA_MDCCR_48 = 0x0D,
270 MIIDA_MDCCR_54 = 0x0E,
271 MIIDA_MDCCR_60 = 0x0F,
272 };
273
274 DECLARE_GLOBAL_DATA_PTR;
275
npcm750_mdio_read(struct mii_dev * bus,int addr,int devad,int regs)276 static int npcm750_mdio_read(struct mii_dev *bus, int addr, int devad, int regs)
277 {
278 struct npcm750_eth_dev *priv = (struct npcm750_eth_dev *)bus->priv;
279 struct emc_regs *reg = priv->emc_regs_p;
280 u32 start, val;
281 int timeout = CFG_MDIO_TIMEOUT;
282
283 val = (addr << 0x08) | regs | PHYBUSY | (MIIDA_MDCCR_60 << 20);
284 writel(val, ®->miida);
285
286 start = get_timer(0);
287 while (get_timer(start) < timeout) {
288 if (!(readl(®->miida) & PHYBUSY)) {
289 val = readl(®->miid);
290 return val;
291 }
292 udelay(10);
293 };
294 return -ETIMEDOUT;
295 }
296
npcm750_mdio_write(struct mii_dev * bus,int addr,int devad,int regs,u16 val)297 static int npcm750_mdio_write(struct mii_dev *bus, int addr, int devad, int regs,
298 u16 val)
299 {
300 struct npcm750_eth_dev *priv = (struct npcm750_eth_dev *)bus->priv;
301 struct emc_regs *reg = priv->emc_regs_p;
302 ulong start;
303 int ret = -ETIMEDOUT, timeout = CFG_MDIO_TIMEOUT;
304
305 writel(val, ®->miid);
306 writel((addr << 0x08) | regs | PHYBUSY | PHYWR | (MIIDA_MDCCR_60 << 20), ®->miida);
307
308 start = get_timer(0);
309 while (get_timer(start) < timeout) {
310 if (!(readl(®->miida) & PHYBUSY)) {
311 ret = 0;
312 break;
313 }
314 udelay(10);
315 };
316 return ret;
317 }
318
npcm750_mdio_reset(struct mii_dev * bus)319 static int npcm750_mdio_reset(struct mii_dev *bus)
320 {
321 return 0;
322 }
323
npcm750_mdio_init(const char * name,struct npcm750_eth_dev * priv)324 static int npcm750_mdio_init(const char *name, struct npcm750_eth_dev *priv)
325 {
326 struct emc_regs *reg = priv->emc_regs_p;
327 struct mii_dev *bus = mdio_alloc();
328
329 if (!bus) {
330 printf("Failed to allocate MDIO bus\n");
331 return -ENOMEM;
332 }
333
334 bus->read = npcm750_mdio_read;
335 bus->write = npcm750_mdio_write;
336 snprintf(bus->name, sizeof(bus->name), "%s", name);
337 bus->reset = npcm750_mdio_reset;
338
339 bus->priv = (void *)priv;
340
341 writel(readl(®->mcmdr) | MCMDR_ENMDC, ®->mcmdr);
342 return mdio_register(bus);
343 }
344
npcm750_tx_descs_init(struct npcm750_eth_dev * priv)345 static void npcm750_tx_descs_init(struct npcm750_eth_dev *priv)
346 {
347 struct emc_regs *reg = priv->emc_regs_p;
348 struct npcm750_txbd *desc_table_p = &priv->tdesc[0];
349 struct npcm750_txbd *desc_p;
350 u8 *txbuffs = &priv->txbuffs[0];
351 u32 idx;
352
353 writel((u32)desc_table_p, ®->txdlsa);
354 priv->curr_txd = desc_table_p;
355
356 for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) {
357 desc_p = &desc_table_p[idx];
358 desc_p->buffer = (u32)&txbuffs[idx * PKTSIZE_ALIGN];
359 desc_p->sl = 0;
360 desc_p->mode = 0;
361 desc_p->mode = TX_OWEN_CPU | PADDINGMODE | CRCMODE | MACTXINTEN;
362 if (idx < (CFG_TX_DESCR_NUM - 1))
363 desc_p->next = (u32)&desc_table_p[idx + 1];
364 else
365 desc_p->next = (u32)&priv->tdesc[0];
366 }
367 flush_dcache_range((ulong)&desc_table_p[0],
368 (ulong)&desc_table_p[CFG_TX_DESCR_NUM]);
369 }
370
npcm750_rx_descs_init(struct npcm750_eth_dev * priv)371 static void npcm750_rx_descs_init(struct npcm750_eth_dev *priv)
372 {
373 struct emc_regs *reg = priv->emc_regs_p;
374 struct npcm750_rxbd *desc_table_p = &priv->rdesc[0];
375 struct npcm750_rxbd *desc_p;
376 u8 *rxbuffs = &priv->rxbuffs[0];
377 u32 idx;
378
379 flush_dcache_range((ulong)priv->rxbuffs[0],
380 (ulong)priv->rxbuffs[CFG_RX_DESCR_NUM]);
381
382 writel((u32)desc_table_p, ®->rxdlsa);
383 priv->curr_rxd = desc_table_p;
384
385 for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) {
386 desc_p = &desc_table_p[idx];
387 desc_p->sl = RX_OWEN_DMA;
388 desc_p->buffer = (u32)&rxbuffs[idx * PKTSIZE_ALIGN];
389 if (idx < (CFG_RX_DESCR_NUM - 1))
390 desc_p->next = (u32)&desc_table_p[idx + 1];
391 else
392 desc_p->next = (u32)&priv->rdesc[0];
393 }
394 flush_dcache_range((ulong)&desc_table_p[0],
395 (ulong)&desc_table_p[CFG_RX_DESCR_NUM]);
396 }
397
npcm750_set_fifo_threshold(struct npcm750_eth_dev * priv)398 static void npcm750_set_fifo_threshold(struct npcm750_eth_dev *priv)
399 {
400 struct emc_regs *reg = priv->emc_regs_p;
401 unsigned int val;
402
403 val = RXTHD | TXTHD | BLENGTH;
404 writel(val, ®->fftcr);
405 }
406
npcm750_set_global_maccmd(struct npcm750_eth_dev * priv)407 static void npcm750_set_global_maccmd(struct npcm750_eth_dev *priv)
408 {
409 struct emc_regs *reg = priv->emc_regs_p;
410 unsigned int val;
411
412 val = readl(®->mcmdr);
413 val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | MCMDR_NDEF;
414 writel(val, ®->mcmdr);
415 }
416
npcm750_set_cam(struct npcm750_eth_dev * priv,unsigned int x,unsigned char * pval)417 static void npcm750_set_cam(struct npcm750_eth_dev *priv,
418 unsigned int x, unsigned char *pval)
419 {
420 struct emc_regs *reg = priv->emc_regs_p;
421 unsigned int msw, lsw;
422
423 msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3];
424 lsw = (pval[4] << 24) | (pval[5] << 16);
425
426 writel(lsw, ®->cam0l + x * CAM_ENTRY_SIZE);
427 writel(msw, ®->cam0m + x * CAM_ENTRY_SIZE);
428 writel(readl(®->camen) | CAM0EN, ®->camen);
429 writel(CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AUP, ®->camcmr);
430 }
431
npcm750_adjust_link(struct emc_regs * reg,struct phy_device * phydev)432 static void npcm750_adjust_link(struct emc_regs *reg,
433 struct phy_device *phydev)
434 {
435 u32 val = readl(®->mcmdr);
436
437 if (!phydev->link) {
438 printf("%s: No link.\n", phydev->dev->name);
439 return;
440 }
441
442 if (phydev->speed == 100)
443 val |= MCMDR_OPMOD;
444 else
445 val &= ~MCMDR_OPMOD;
446
447 if (phydev->duplex)
448 val |= MCMDR_FDUP;
449 else
450 val &= ~MCMDR_FDUP;
451
452 writel(val, ®->mcmdr);
453
454 debug("Speed: %d, %s duplex%s\n", phydev->speed,
455 (phydev->duplex) ? "full" : "half",
456 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
457 }
458
npcm750_phy_init(struct npcm750_eth_dev * priv,void * dev)459 static int npcm750_phy_init(struct npcm750_eth_dev *priv, void *dev)
460 {
461 struct phy_device *phydev;
462 int ret;
463 u32 address = 0x0;
464
465 phydev = phy_connect(priv->bus, address, dev, priv->interface);
466 if (!phydev)
467 return -ENODEV;
468
469 if (priv->max_speed) {
470 ret = phy_set_supported(phydev, priv->max_speed);
471 if (ret)
472 return ret;
473 }
474 phydev->advertising = phydev->supported;
475
476 priv->phydev = phydev;
477 phy_config(phydev);
478 return 0;
479 }
480
npcm750_eth_start(struct udevice * dev)481 static int npcm750_eth_start(struct udevice *dev)
482 {
483 struct eth_pdata *pdata = dev_get_plat(dev);
484 struct npcm750_eth_dev *priv = dev_get_priv(dev);
485 struct emc_regs *reg = priv->emc_regs_p;
486 u8 *enetaddr = pdata->enetaddr;
487 int ret;
488
489 writel(readl(®->mcmdr) & ~MCMDR_TXON & ~MCMDR_RXON, ®->mcmdr);
490
491 writel(readl(®->mcmdr) | MCMDR_SWR, ®->mcmdr);
492 do {
493 ret = readl(®->mcmdr);
494 } while (ret & MCMDR_SWR);
495
496 npcm750_rx_descs_init(priv);
497 npcm750_tx_descs_init(priv);
498
499 npcm750_set_cam(priv, priv->idx, enetaddr);
500 npcm750_set_global_maccmd(priv);
501 npcm750_set_fifo_threshold(priv);
502
503 /* Start up the PHY */
504 ret = phy_startup(priv->phydev);
505 if (ret) {
506 printf("Could not initialize PHY\n");
507 return ret;
508 }
509
510 npcm750_adjust_link(reg, priv->phydev);
511 writel(readl(®->mcmdr) | MCMDR_TXON | MCMDR_RXON, ®->mcmdr);
512
513 return 0;
514 }
515
npcm750_eth_send(struct udevice * dev,void * packet,int length)516 static int npcm750_eth_send(struct udevice *dev, void *packet, int length)
517 {
518 struct npcm750_eth_dev *priv = dev_get_priv(dev);
519 struct emc_regs *reg = priv->emc_regs_p;
520 struct npcm750_txbd *desc_p;
521 struct npcm750_txbd *next_desc_p;
522
523 desc_p = priv->curr_txd;
524
525 invalidate_dcache_range((ulong)desc_p, (ulong)(desc_p + 1));
526 /* Check if the descriptor is owned by CPU */
527 if (desc_p->mode & TX_OWEN_DMA) {
528 next_desc_p = (struct npcm750_txbd *)desc_p->next;
529
530 while ((next_desc_p != desc_p) && (next_desc_p->mode & TX_OWEN_DMA))
531 next_desc_p = (struct npcm750_txbd *)next_desc_p->next;
532
533 if (next_desc_p == desc_p) {
534 struct emc_regs *reg = priv->emc_regs_p;
535
536 writel(0, ®->tsdr);
537 serial_printf("TX: overflow and exit\n");
538 return -EPERM;
539 }
540
541 desc_p = next_desc_p;
542 }
543
544 memcpy((void *)desc_p->buffer, packet, length);
545 flush_dcache_range((ulong)desc_p->buffer,
546 (ulong)desc_p->buffer + roundup(length, ARCH_DMA_MINALIGN));
547 desc_p->sl = 0;
548 desc_p->sl = length & TX_STAT_TBC;
549 desc_p->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE;
550 flush_dcache_range((ulong)desc_p, (ulong)(desc_p + 1));
551
552 if (!(readl(®->mcmdr) & MCMDR_TXON))
553 writel(readl(®->mcmdr) | MCMDR_TXON, ®->mcmdr);
554 priv->curr_txd = (struct npcm750_txbd *)priv->curr_txd->next;
555
556 writel(0, ®->tsdr);
557 return 0;
558 }
559
npcm750_eth_recv(struct udevice * dev,int flags,uchar ** packetp)560 static int npcm750_eth_recv(struct udevice *dev, int flags, uchar **packetp)
561 {
562 struct npcm750_eth_dev *priv = dev_get_priv(dev);
563 struct npcm750_rxbd *desc_p;
564 struct npcm750_rxbd *next_desc_p;
565 int length = -1;
566
567 desc_p = priv->curr_rxd;
568 invalidate_dcache_range((ulong)desc_p, (ulong)(desc_p + 1));
569
570 if ((desc_p->sl & RX_STAT_OWNER) == RX_OWEN_DMA) {
571 next_desc_p = (struct npcm750_rxbd *)desc_p->next;
572 while ((next_desc_p != desc_p) &&
573 ((next_desc_p->sl & RX_STAT_OWNER) == RX_OWEN_CPU)) {
574 next_desc_p = (struct npcm750_rxbd *)next_desc_p->next;
575 }
576
577 if (next_desc_p == desc_p) {
578 struct emc_regs *reg = priv->emc_regs_p;
579
580 writel(0, ®->rsdr);
581 serial_printf("RX: overflow and exit\n");
582 return -EPERM;
583 }
584 desc_p = next_desc_p;
585 }
586
587 /* Check if the descriptor is owned by CPU */
588 if ((desc_p->sl & RX_STAT_OWNER) == RX_OWEN_CPU) {
589 if (desc_p->sl & RX_STAT_RXGD) {
590 length = desc_p->sl & RX_STAT_RBC;
591 invalidate_dcache_range((ulong)desc_p->buffer,
592 (ulong)(desc_p->buffer + roundup(length,
593 ARCH_DMA_MINALIGN)));
594 *packetp = (u8 *)(u32)desc_p->buffer;
595 priv->curr_rxd = desc_p;
596 }
597 }
598 return length;
599 }
600
npcm750_eth_free_pkt(struct udevice * dev,uchar * packet,int length)601 static int npcm750_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
602 {
603 struct npcm750_eth_dev *priv = dev_get_priv(dev);
604 struct emc_regs *reg = priv->emc_regs_p;
605 struct npcm750_rxbd *desc_p = priv->curr_rxd;
606
607 /*
608 * Make the current descriptor valid again and go to
609 * the next one
610 */
611 desc_p->sl |= RX_OWEN_DMA;
612 flush_dcache_range((ulong)desc_p, (ulong)(desc_p + 1));
613 priv->curr_rxd = (struct npcm750_rxbd *)priv->curr_rxd->next;
614 writel(0, ®->rsdr);
615
616 return 0;
617 }
618
npcm750_eth_stop(struct udevice * dev)619 static void npcm750_eth_stop(struct udevice *dev)
620 {
621 struct npcm750_eth_dev *priv = dev_get_priv(dev);
622 struct emc_regs *reg = priv->emc_regs_p;
623
624 writel(readl(®->mcmdr) & ~MCMDR_TXON, ®->mcmdr);
625 writel(readl(®->mcmdr) & ~MCMDR_RXON, ®->mcmdr);
626 priv->curr_txd = (struct npcm750_txbd *)readl(®->txdlsa);
627 priv->curr_rxd = (struct npcm750_rxbd *)readl(®->rxdlsa);
628 phy_shutdown(priv->phydev);
629 }
630
npcm750_eth_write_hwaddr(struct udevice * dev)631 static int npcm750_eth_write_hwaddr(struct udevice *dev)
632 {
633 struct eth_pdata *pdata = dev_get_plat(dev);
634 struct npcm750_eth_dev *priv = dev_get_priv(dev);
635
636 npcm750_set_cam(priv, CAM0, pdata->enetaddr);
637 return 0;
638 }
639
npcm750_eth_bind(struct udevice * dev)640 static int npcm750_eth_bind(struct udevice *dev)
641 {
642 return 0;
643 }
644
npcm750_eth_probe(struct udevice * dev)645 static int npcm750_eth_probe(struct udevice *dev)
646 {
647 struct eth_pdata *pdata = dev_get_plat(dev);
648 struct npcm750_eth_dev *priv = dev_get_priv(dev);
649 u32 iobase = pdata->iobase;
650 int ret;
651
652 memset(priv, 0, sizeof(struct npcm750_eth_dev));
653 ret = dev_read_u32(dev, "id", &priv->idx);
654 if (ret) {
655 printf("failed to get id\n");
656 return -EINVAL;
657 }
658
659 priv->gcr_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-gcr");
660 if (IS_ERR(priv->gcr_regmap))
661 return -EINVAL;
662
663 priv->emc_regs_p = (struct emc_regs *)iobase;
664 priv->interface = pdata->phy_interface;
665 priv->max_speed = pdata->max_speed;
666
667 if (priv->idx == 0) {
668 /* Enable RMII for EMC1 module */
669 regmap_update_bits(priv->gcr_regmap, GCR_INTCR, INTCR_R1EN, INTCR_R1EN);
670 }
671
672 npcm750_mdio_init(dev->name, priv);
673 priv->bus = miiphy_get_dev_by_name(dev->name);
674
675 ret = npcm750_phy_init(priv, dev);
676
677 return ret;
678 }
679
npcm750_eth_remove(struct udevice * dev)680 static int npcm750_eth_remove(struct udevice *dev)
681 {
682 struct npcm750_eth_dev *priv = dev_get_priv(dev);
683
684 free(priv->phydev);
685 mdio_unregister(priv->bus);
686 mdio_free(priv->bus);
687
688 return 0;
689 }
690
691 static const struct eth_ops npcm750_eth_ops = {
692 .start = npcm750_eth_start,
693 .send = npcm750_eth_send,
694 .recv = npcm750_eth_recv,
695 .free_pkt = npcm750_eth_free_pkt,
696 .stop = npcm750_eth_stop,
697 .write_hwaddr = npcm750_eth_write_hwaddr,
698 };
699
npcm750_eth_ofdata_to_platdata(struct udevice * dev)700 static int npcm750_eth_ofdata_to_platdata(struct udevice *dev)
701 {
702 struct npcm750_eth_pdata *npcm750_pdata = dev_get_plat(dev);
703 struct eth_pdata *pdata = &npcm750_pdata->eth_pdata;
704 const char *phy_mode;
705 const fdt32_t *cell;
706 int ret = 0;
707
708 pdata->iobase = (phys_addr_t)dev_read_addr_ptr(dev);
709
710 pdata->phy_interface = -1;
711 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", NULL);
712
713 if (phy_mode)
714 pdata->phy_interface = dev_read_phy_mode(dev);
715
716 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
717 return -EINVAL;
718
719 pdata->max_speed = 0;
720 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
721 if (cell)
722 pdata->max_speed = fdt32_to_cpu(*cell);
723
724 return ret;
725 }
726
727 static const struct udevice_id npcm750_eth_ids[] = {
728 { .compatible = "nuvoton,npcm750-emc" },
729 { }
730 };
731
732 U_BOOT_DRIVER(eth_npcm750) = {
733 .name = "eth_npcm750",
734 .id = UCLASS_ETH,
735 .of_match = npcm750_eth_ids,
736 .of_to_plat = npcm750_eth_ofdata_to_platdata,
737 .bind = npcm750_eth_bind,
738 .probe = npcm750_eth_probe,
739 .remove = npcm750_eth_remove,
740 .ops = &npcm750_eth_ops,
741 .priv_auto = sizeof(struct npcm750_eth_dev),
742 .plat_auto = sizeof(struct npcm750_eth_pdata),
743 .flags = DM_FLAG_ALLOC_PRIV_DMA,
744 };
745