1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* linux/arch/arm/plat-s3c/include/plat/regs-otg.h 3 * 4 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at> 5 * 6 * Registers remapping: 7 * Lukasz Majewski <l.majewski@samsumg.com> 8 */ 9 10 #ifndef __ASM_ARCH_REGS_USB_OTG_HS_H 11 #define __ASM_ARCH_REGS_USB_OTG_HS_H 12 13 #include "../common/dwc2_core.h" 14 15 struct dwc2_usbotg_phy { 16 u32 phypwr; 17 u32 phyclk; 18 u32 rstcon; 19 }; 20 21 #define FULL_SPEED_CONTROL_PKT_SIZE 8 22 #define FULL_SPEED_BULK_PKT_SIZE 64 23 24 #define HIGH_SPEED_CONTROL_PKT_SIZE 64 25 #define HIGH_SPEED_BULK_PKT_SIZE 512 26 27 #define RX_FIFO_SIZE 1024 28 #define NPTX_FIFO_SIZE 1024 29 #define PTX_FIFO_SIZE 384 30 31 #define USB_PHY_CTRL_EN0 BIT(0) 32 33 /* OPHYPWR */ 34 #define PHY_0_SLEEP BIT(5) 35 #define OTG_DISABLE_0 BIT(4) 36 #define ANALOG_PWRDOWN BIT(3) 37 #define FORCE_SUSPEND_0 BIT(0) 38 39 /* URSTCON */ 40 #define HOST_SW_RST BIT(4) 41 #define PHY_SW_RST1 BIT(3) 42 #define PHYLNK_SW_RST BIT(2) 43 #define LINK_SW_RST BIT(1) 44 #define PHY_SW_RST0 BIT(0) 45 46 /* OPHYCLK */ 47 #define COMMON_ON_N1 BIT(7) 48 #define COMMON_ON_N0 BIT(4) 49 #define ID_PULLUP0 BIT(2) 50 #define CLK_SEL_24MHZ (0x3 << 0) 51 #define CLK_SEL_12MHZ (0x2 << 0) 52 #define CLK_SEL_48MHZ (0x0 << 0) 53 54 #define EXYNOS4X12_ID_PULLUP0 BIT(3) 55 #define EXYNOS4X12_COMMON_ON_N0 BIT(4) 56 #define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0) 57 #define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0) 58 59 /* Masks definitions */ 60 #define GINTMSK_INIT (GINTSTS_WKUPINT | GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_ENUMDONE | \ 61 GINTSTS_USBRST | GINTSTS_USBSUSP | GINTSTS_OTGINT) 62 #define DOEPMSK_INIT (DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | DOEPMSK_XFERCOMPLMSK) 63 #define DIEPMSK_INIT (DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | DIEPMSK_XFERCOMPLMSK) 64 #define GAHBCFG_INIT (GAHBCFG_DMA_EN | \ 65 FIELD_PREP(GAHBCFG_HBSTLEN_MASK, GAHBCFG_HBSTLEN_INCR4) | \ 66 GAHBCFG_GLBL_INTR_EN) 67 68 #endif 69