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Searched refs:GATE (Results 1 – 22 of 22) sorted by relevance

/drivers/clk/sunxi/
A Dclk_r40.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
20 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
26 [CLK_BUS_OTG] = GATE(0x060, BIT(25)),
60 [CLK_NAND] = GATE(0x080, BIT(31)),
61 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
62 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
63 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
64 [CLK_SPI3] = GATE(0x0ac, BIT(31)),
[all …]
A Dclk_a10.c16 [CLK_AHB_OTG] = GATE(0x060, BIT(0)),
17 [CLK_AHB_EHCI0] = GATE(0x060, BIT(1)),
18 [CLK_AHB_OHCI0] = GATE(0x060, BIT(2)),
19 [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)),
21 [CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
22 [CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
50 [CLK_NAND] = GATE(0x080, BIT(31)),
51 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
52 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
53 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
[all …]
A Dclk_h616.c19 [CLK_DE] = GATE(0x600, BIT(31)),
20 [CLK_BUS_DE] = GATE(0x60c, BIT(0)),
22 [CLK_NAND0] = GATE(0x810, BIT(31)),
23 [CLK_NAND1] = GATE(0x814, BIT(31)),
24 [CLK_BUS_NAND] = GATE(0x82c, BIT(0)),
26 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
27 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
28 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
43 [CLK_SPI0] = GATE(0x940, BIT(31)),
44 [CLK_SPI1] = GATE(0x944, BIT(31)),
[all …]
A Dclk_h6.c20 [CLK_DE] = GATE(0x600, BIT(31)),
21 [CLK_BUS_DE] = GATE(0x60c, BIT(0)),
23 [CLK_NAND0] = GATE(0x810, BIT(31)),
24 [CLK_NAND1] = GATE(0x814, BIT(31)),
25 [CLK_BUS_NAND] = GATE(0x82c, BIT(0)),
27 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
28 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
29 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
40 [CLK_SPI0] = GATE(0x940, BIT(31)),
41 [CLK_SPI1] = GATE(0x944, BIT(31)),
[all …]
A Dclk_a64.c19 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
20 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
21 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
26 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
35 [CLK_BUS_DE] = GATE(0x064, BIT(12)),
37 [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
48 [CLK_NAND] = GATE(0x080, BIT(31)),
49 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
50 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
59 [CLK_DE] = GATE(0x104, BIT(31)),
[all …]
A Dclk_h3.c18 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
19 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
20 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
21 [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
22 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
25 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
52 [CLK_NAND] = GATE(0x080, BIT(31)),
53 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
54 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
65 [CLK_DE] = GATE(0x104, BIT(31)),
[all …]
A Dclk_a31.c16 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
34 [CLK_APB1_PIO] = GATE(0x068, BIT(5)),
47 [CLK_NAND0] = GATE(0x080, BIT(31)),
48 [CLK_NAND1] = GATE(0x084, BIT(31)),
49 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
50 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
51 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
[all …]
A Dclk_a83t.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
20 [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
24 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
32 [CLK_BUS_DE] = GATE(0x064, BIT(12)),
34 [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
45 [CLK_NAND] = GATE(0x080, BIT(31)),
46 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
47 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
[all …]
A Dclk_a10s.c16 [CLK_AHB_OTG] = GATE(0x060, BIT(0)),
17 [CLK_AHB_EHCI] = GATE(0x060, BIT(1)),
18 [CLK_AHB_OHCI] = GATE(0x060, BIT(2)),
19 [CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
20 [CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
21 [CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
28 [CLK_APB0_PIO] = GATE(0x068, BIT(5)),
38 [CLK_NAND] = GATE(0x080, BIT(31)),
39 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
40 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
[all …]
A Dclk_a100.c16 [CLK_DE] = GATE(0x600, BIT(31)),
17 [CLK_BUS_DE] = GATE(0x60c, BIT(0)),
19 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
20 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
21 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
23 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
29 [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
30 [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
34 [CLK_SPI0] = GATE(0x940, BIT(31)),
35 [CLK_SPI1] = GATE(0x944, BIT(31)),
[all …]
A Dclk_a80.c16 [CLK_NAND0_0] = GATE(0x400, BIT(31)),
17 [CLK_NAND0_1] = GATE(0x404, BIT(31)),
18 [CLK_NAND1_0] = GATE(0x408, BIT(31)),
20 [CLK_SPI0] = GATE(0x430, BIT(31)),
21 [CLK_SPI1] = GATE(0x434, BIT(31)),
22 [CLK_SPI2] = GATE(0x438, BIT(31)),
23 [CLK_SPI3] = GATE(0x43c, BIT(31)),
71 [0] = GATE(0x0, BIT(16)),
72 [1] = GATE(0x4, BIT(16)),
73 [2] = GATE(0x8, BIT(16)),
[all …]
A Dclk_a523.c19 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
20 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
21 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
22 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
23 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
24 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
28 [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
29 [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
30 [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
32 [CLK_SPI0] = GATE(0x940, BIT(31)),
[all …]
A Dclk_a23.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
26 [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
28 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
37 [CLK_NAND] = GATE(0x080, BIT(31)),
38 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
[all …]
A Dclk_d1.c17 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
18 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
19 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
20 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
21 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
22 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
26 [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
27 [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
30 [CLK_SPI0] = GATE(0x940, BIT(31)),
31 [CLK_SPI1] = GATE(0x944, BIT(31)),
[all …]
A Dclk_v3s.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
21 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
24 [CLK_BUS_DE] = GATE(0x064, BIT(12)),
26 [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
28 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
36 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
40 [CLK_DE] = GATE(0x104, BIT(31)),
[all …]
A Dclk_f1c100s.c14 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
15 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
16 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
17 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
18 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
20 [CLK_BUS_I2C0] = GATE(0x068, BIT(16)),
21 [CLK_BUS_I2C1] = GATE(0x068, BIT(17)),
22 [CLK_BUS_I2C2] = GATE(0x068, BIT(18)),
23 [CLK_BUS_PIO] = GATE(0x068, BIT(19)),
25 [CLK_BUS_UART0] = GATE(0x06c, BIT(20)),
[all …]
A Dclk_h6_r.c16 [CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)),
17 [CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)),
18 [CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)),
19 [CLK_R_APB2_UART] = GATE(0x18c, BIT(0)),
20 [CLK_R_APB2_I2C] = GATE(0x19c, BIT(0)),
21 [CLK_R_APB2_RSB] = GATE(0x1bc, BIT(0)),
22 [CLK_R_APB1_IR] = GATE(0x1cc, BIT(0)),
23 [CLK_R_APB1_W1] = GATE(0x1ec, BIT(0)),
A Dclk_a31_r.c14 [CLK_APB0_PIO] = GATE(0x028, BIT(0)),
15 [CLK_APB0_IR] = GATE(0x028, BIT(1)),
16 [CLK_APB0_TIMER] = GATE(0x028, BIT(2)),
17 [CLK_APB0_RSB] = GATE(0x028, BIT(3)),
18 [CLK_APB0_UART] = GATE(0x028, BIT(4)),
19 [CLK_APB0_I2C] = GATE(0x028, BIT(6)),
20 [CLK_APB0_TWD] = GATE(0x028, BIT(7)),
A Dclk_a523_r.c17 [CLK_BUS_R_TWD] = GATE(0x12c, BIT(0)),
18 [CLK_BUS_R_I2C0] = GATE(0x19c, BIT(0)),
19 [CLK_BUS_R_I2C1] = GATE(0x19c, BIT(1)),
20 [CLK_BUS_R_I2C2] = GATE(0x19c, BIT(2)),
21 [CLK_BUS_R_RTC] = GATE(0x20c, BIT(0)),
/drivers/clk/exynos/
A Dclk-exynos850.c145 GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
147 GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
151 GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
178 GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
207 GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
209 GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart",
211 GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip",
357 GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
362 GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",
430 GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
[all …]
A Dclk.h177 #define GATE(_id, cname, pname, o, b, f, gf) \ macro
/drivers/clk/
A Dclk_k210.c152 GATE(K210_CLK_CPU, K210_SYSCTL_EN_CENT, 0) \
153 GATE(K210_CLK_SRAM0, K210_SYSCTL_EN_CENT, 1) \
154 GATE(K210_CLK_SRAM1, K210_SYSCTL_EN_CENT, 2) \
155 GATE(K210_CLK_APB0, K210_SYSCTL_EN_CENT, 3) \
156 GATE(K210_CLK_APB1, K210_SYSCTL_EN_CENT, 4) \
157 GATE(K210_CLK_APB2, K210_SYSCTL_EN_CENT, 5) \
186 GATE(K210_CLK_RTC, K210_SYSCTL_EN_PERI, 29)
192 #define GATE(id, ...) GATEIFY(id), macro
194 #undef GATE
199 #define GATE(id, _off, _idx) \ macro
[all …]

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