1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2018 Liviu Dudau <liviu@dudau.co.uk>
4 *
5 * Based on the Linux driver, (C) 2012 Texas Instruments
6 */
7
8 #include <dm.h>
9 #include <display.h>
10 #include <i2c.h>
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13
14 /*
15 * TDA19988 uses paged registers. We encode the page# in the upper
16 * bits of the register#. It also means that reads/writes to a register
17 * have to ensure that the register's page is selected as the current
18 * page.
19 */
20 #define REG(page, addr) (((page) << 8) | (addr))
21 #define REG2ADDR(reg) ((reg) & 0xff)
22 #define REG2PAGE(reg) (((reg) >> 8) & 0xff)
23
24 /* register for setting current page */
25 #define REG_CURRENT_PAGE 0xff
26
27 /* Page 00h: General Control */
28 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
29 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
30 #define MAIN_CNTRL0_SR BIT(0)
31 #define MAIN_CNTRL0_DECS BIT(1)
32 #define MAIN_CNTRL0_DEHS BIT(2)
33 #define MAIN_CNTRL0_CECS BIT(3)
34 #define MAIN_CNTRL0_CEHS BIT(4)
35 #define MAIN_CNTRL0_SCALER BIT(7)
36 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
37 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
38 #define SOFTRESET_AUDIO BIT(0)
39 #define SOFTRESET_I2C_MASTER BIT(1)
40 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
41 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
42 #define I2C_MASTER_DIS_MM BIT(0)
43 #define I2C_MASTER_DIS_FILT BIT(1)
44 #define I2C_MASTER_APP_STRT_LAT BIT(2)
45 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
46 #define FEAT_POWERDOWN_PREFILT BIT(0)
47 #define FEAT_POWERDOWN_CSC BIT(1)
48 #define FEAT_POWERDOWN_SPDIF BIT(3)
49 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
50 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
51 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
52 #define INT_FLAGS_2_EDID_BLK_RD BIT(1)
53 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
54 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
55 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
56 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
57 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
58 #define VIP_CNTRL_0_MIRR_A BIT(7)
59 #define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
60 #define VIP_CNTRL_0_MIRR_B BIT(3)
61 #define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
62 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
63 #define VIP_CNTRL_1_MIRR_C BIT(7)
64 #define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
65 #define VIP_CNTRL_1_MIRR_D BIT(3)
66 #define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
67 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
68 #define VIP_CNTRL_2_MIRR_E BIT(7)
69 #define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
70 #define VIP_CNTRL_2_MIRR_F BIT(3)
71 #define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
72 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
73 #define VIP_CNTRL_3_X_TGL BIT(0)
74 #define VIP_CNTRL_3_H_TGL BIT(1)
75 #define VIP_CNTRL_3_V_TGL BIT(2)
76 #define VIP_CNTRL_3_EMB BIT(3)
77 #define VIP_CNTRL_3_SYNC_DE BIT(4)
78 #define VIP_CNTRL_3_SYNC_HS BIT(5)
79 #define VIP_CNTRL_3_DE_INT BIT(6)
80 #define VIP_CNTRL_3_EDGE BIT(7)
81 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
82 #define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
83 #define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
84 #define VIP_CNTRL_4_CCIR656 BIT(4)
85 #define VIP_CNTRL_4_656_ALT BIT(5)
86 #define VIP_CNTRL_4_TST_656 BIT(6)
87 #define VIP_CNTRL_4_TST_PAT BIT(7)
88 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
89 #define VIP_CNTRL_5_CKCASE BIT(0)
90 #define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
91 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
92 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
93 #define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
94 #define MAT_CONTRL_MAT_BP BIT(2)
95 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
96 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
97 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
98 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
99 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
100 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
101 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
102 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
103 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
104 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
105 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
106 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
107 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
108 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
109 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
110 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
111 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
112 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
113 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
114 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
115 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
116 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
117 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
118 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
119 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
120 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
121 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
122 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
123 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
124 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
125 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
126 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
127 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
128 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
129 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
130 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
131 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
132 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
133 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
134 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
135 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
136 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
137 #define TBG_CNTRL_0_TOP_TGL BIT(0)
138 #define TBG_CNTRL_0_TOP_SEL BIT(1)
139 #define TBG_CNTRL_0_DE_EXT BIT(2)
140 #define TBG_CNTRL_0_TOP_EXT BIT(3)
141 #define TBG_CNTRL_0_FRAME_DIS BIT(5)
142 #define TBG_CNTRL_0_SYNC_MTHD BIT(6)
143 #define TBG_CNTRL_0_SYNC_ONCE BIT(7)
144 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
145 #define TBG_CNTRL_1_H_TGL BIT(0)
146 #define TBG_CNTRL_1_V_TGL BIT(1)
147 #define TBG_CNTRL_1_TGL_EN BIT(2)
148 #define TBG_CNTRL_1_X_EXT BIT(3)
149 #define TBG_CNTRL_1_H_EXT BIT(4)
150 #define TBG_CNTRL_1_V_EXT BIT(5)
151 #define TBG_CNTRL_1_DWIN_DIS BIT(6)
152 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
153 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
154 #define HVF_CNTRL_0_SM BIT(7)
155 #define HVF_CNTRL_0_RWB BIT(6)
156 #define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
157 #define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
158 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
159 #define HVF_CNTRL_1_FOR BIT(0)
160 #define HVF_CNTRL_1_YUVBLK BIT(1)
161 #define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
162 #define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
163 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
164 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
165 #define AIP_CLKSEL_AIP_SPDIF (0 << 3)
166 #define AIP_CLKSEL_AIP_I2S BIT(3)
167 #define AIP_CLKSEL_FS_ACLK (0 << 0)
168 #define AIP_CLKSEL_FS_MCLK BIT(0)
169
170 /* Page 02h: PLL settings */
171 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
172 #define PLL_SERIAL_1_SRL_FDN BIT(0)
173 #define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
174 #define PLL_SERIAL_1_SRL_MAN_IZ BIT(6)
175 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
176 #define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
177 #define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
178 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
179 #define PLL_SERIAL_3_SRL_CCIR BIT(0)
180 #define PLL_SERIAL_3_SRL_DE BIT(2)
181 #define PLL_SERIAL_3_SRL_PXIN_SEL BIT(4)
182 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
183 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
184 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
185 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
186 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
187 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
188 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
189 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
190 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
191 #define AUDIO_DIV_SERCLK_1 0
192 #define AUDIO_DIV_SERCLK_2 1
193 #define AUDIO_DIV_SERCLK_4 2
194 #define AUDIO_DIV_SERCLK_8 3
195 #define AUDIO_DIV_SERCLK_16 4
196 #define AUDIO_DIV_SERCLK_32 5
197 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
198 #define SEL_CLK_SEL_CLK1 BIT(0)
199 #define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
200 #define SEL_CLK_ENA_SC_CLK BIT(3)
201 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
202
203 /* Page 09h: EDID Control */
204 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
205 /* next 127 successive registers are the EDID block */
206 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
207 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
208 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
209 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
210 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
211
212 /* Page 11h: audio settings and content info packets */
213 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
214 #define AIP_CNTRL_0_RST_FIFO BIT(0)
215 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
216 #define ENC_CNTRL_RST_ENC BIT(0)
217 #define ENC_CNTRL_RST_SEL BIT(1)
218 #define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
219
220 /* Page 12h: HDCP and OTP */
221 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
222 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
223 #define TX4_PD_RAM BIT(1)
224 #define REG_TX33 REG(0x12, 0xb8) /* read/write */
225 #define TX33_HDMI BIT(1)
226
227 /* CEC registers, not paged */
228 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
229 #define CEC_FRO_IM_CLK_CTRL_GHOST_DIS BIT(7)
230 #define CEC_FRO_IM_CLK_CTRL_ENA_OTP BIT(6)
231 #define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL BIT(1)
232 #define CEC_FRO_IM_CLK_CTRL_FRO_DIV BIT(0)
233 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
234 #define REG_CEC_RXSHPDINT 0xfd /* read */
235 #define CEC_RXSHPDINT_RXSENS BIT(0)
236 #define CEC_RXSHPDINT_HPD BIT(1)
237 #define TDA19988_CEC_ENAMODS 0xff /* read/write */
238 #define CEC_ENAMODS_EN_RXSENS BIT(2)
239 #define CEC_ENAMODS_EN_HDMI BIT(1)
240 #define CEC_ENAMODS_EN_CEC BIT(0)
241
242 /* Device versions */
243 #define TDA9989N2 0x0101
244 #define TDA19989 0x0201
245 #define TDA19989N2 0x0202
246 #define TDA19988 0x0301
247
248 struct tda19988_priv {
249 struct udevice *chip;
250 struct udevice *cec_chip;
251 u16 revision;
252 u8 current_page;
253 };
254
tda19988_register_set(struct tda19988_priv * priv,u16 reg,u8 val)255 static void tda19988_register_set(struct tda19988_priv *priv, u16 reg, u8 val)
256 {
257 u8 old_val, page = REG2PAGE(reg);
258
259 if (priv->current_page != page) {
260 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
261 priv->current_page = page;
262 }
263 old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
264 old_val |= val;
265 dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val);
266 }
267
tda19988_register_clear(struct tda19988_priv * priv,u16 reg,u8 val)268 static void tda19988_register_clear(struct tda19988_priv *priv, u16 reg, u8 val)
269 {
270 u8 old_val, page = REG2PAGE(reg);
271
272 if (priv->current_page != page) {
273 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
274 priv->current_page = page;
275 }
276 old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
277 old_val &= ~val;
278 dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val);
279 }
280
tda19988_register_write(struct tda19988_priv * priv,u16 reg,u8 val)281 static void tda19988_register_write(struct tda19988_priv *priv, u16 reg, u8 val)
282 {
283 u8 page = REG2PAGE(reg);
284
285 if (priv->current_page != page) {
286 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
287 priv->current_page = page;
288 }
289 dm_i2c_reg_write(priv->chip, REG2ADDR(reg), val);
290 }
291
tda19988_register_read(struct tda19988_priv * priv,u16 reg)292 static int tda19988_register_read(struct tda19988_priv *priv, u16 reg)
293 {
294 u8 page = REG2PAGE(reg);
295
296 if (priv->current_page != page) {
297 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
298 priv->current_page = page;
299 }
300 return dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
301 }
302
tda19988_register_write16(struct tda19988_priv * priv,u16 reg,u16 val)303 static void tda19988_register_write16(struct tda19988_priv *priv,
304 u16 reg, u16 val)
305 {
306 u8 buf[] = { val >> 8, val }, page = REG2PAGE(reg);
307
308 if (priv->current_page != page) {
309 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
310 priv->current_page = page;
311 }
312 dm_i2c_write(priv->chip, REG2ADDR(reg), buf, 2);
313 }
314
tda19988_read_edid(struct udevice * dev,u8 * buf,int buf_size)315 static int tda19988_read_edid(struct udevice *dev, u8 *buf, int buf_size)
316 {
317 struct tda19988_priv *priv = dev_get_priv(dev);
318 int i, val = 0, offset = 0;
319
320 /*
321 * The TDA998x has a problem when trying to read the EDID close to a
322 * HPD assertion: it needs a delay of 100ms to avoid timing out while
323 * trying to read EDID data.
324 */
325 mdelay(120);
326
327 if (priv->revision == TDA19988)
328 tda19988_register_clear(priv, REG_TX4, TX4_PD_RAM);
329
330 while (offset < buf_size) {
331 tda19988_register_write(priv, REG_DDC_ADDR, 0xa0);
332 tda19988_register_write(priv, REG_DDC_OFFS, offset);
333 tda19988_register_write(priv, REG_DDC_SEGM_ADDR, 0x60);
334 tda19988_register_write(priv, REG_DDC_SEGM, 0);
335
336 /* enable reading EDID */
337 tda19988_register_write(priv, REG_EDID_CTRL, 1);
338
339 /* flags must be cleared by software */
340 tda19988_register_write(priv, REG_EDID_CTRL, 0);
341
342 /* wait for block read to complete */
343 for (i = 300; i > 0; i--) {
344 mdelay(1);
345 val = tda19988_register_read(priv, REG_INT_FLAGS_2);
346 if (val < 0)
347 return val;
348 if (val & INT_FLAGS_2_EDID_BLK_RD)
349 break;
350 }
351
352 if (i == 0)
353 return -ETIMEDOUT;
354
355 priv->current_page = REG2PAGE(REG_EDID_DATA_0);
356 dm_i2c_reg_write(priv->chip,
357 REG_CURRENT_PAGE, REG2PAGE(REG_EDID_DATA_0));
358 val = dm_i2c_read(priv->chip,
359 REG2ADDR(REG_EDID_DATA_0), buf + offset, 128);
360 offset += 128;
361 }
362
363 if (priv->revision == TDA19988)
364 tda19988_register_set(priv, REG_TX4, TX4_PD_RAM);
365
366 return offset;
367 }
368
tda19988_enable(struct udevice * dev,int panel_bpp,const struct display_timing * timing)369 static int tda19988_enable(struct udevice *dev, int panel_bpp,
370 const struct display_timing *timing)
371 {
372 struct tda19988_priv *priv = dev_get_priv(dev);
373 u8 div = 148500000 / timing->pixelclock.typ, reg;
374 u16 line_clocks, lines;
375
376 if (dev != 0) {
377 div--;
378 if (div > 3)
379 div = 3;
380 }
381 /* first disable the video ports */
382 tda19988_register_write(priv, REG_ENA_VP_0, 0);
383 tda19988_register_write(priv, REG_ENA_VP_1, 0);
384 tda19988_register_write(priv, REG_ENA_VP_2, 0);
385
386 /* shutdown audio */
387 tda19988_register_write(priv, REG_ENA_AP, 0);
388
389 line_clocks = timing->hsync_len.typ + timing->hback_porch.typ +
390 timing->hactive.typ + timing->hfront_porch.typ;
391 lines = timing->vsync_len.typ + timing->vback_porch.typ +
392 timing->vactive.typ + timing->vfront_porch.typ;
393
394 /* mute the audio FIFO */
395 tda19988_register_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
396 /* HDMI HDCP: off */
397 tda19988_register_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
398 tda19988_register_clear(priv, REG_TX33, TX33_HDMI);
399 tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
400
401 /* no pre-filter or interpolator */
402 tda19988_register_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
403 HVF_CNTRL_0_INTPOL(0));
404 tda19988_register_set(priv, REG_FEAT_POWERDOWN,
405 FEAT_POWERDOWN_PREFILT);
406 tda19988_register_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
407 tda19988_register_write(priv, REG_VIP_CNTRL_4,
408 VIP_CNTRL_4_BLANKIT(0) | VIP_CNTRL_4_BLC(0) |
409 VIP_CNTRL_4_TST_PAT);
410
411 tda19988_register_clear(priv, REG_PLL_SERIAL_1,
412 PLL_SERIAL_1_SRL_MAN_IZ);
413 tda19988_register_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
414 PLL_SERIAL_3_SRL_DE);
415
416 tda19988_register_write(priv, REG_SERIALIZER, 0);
417 tda19988_register_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
418
419 tda19988_register_write(priv, REG_RPT_CNTRL, 0);
420 tda19988_register_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
421 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
422 tda19988_register_write(priv, REG_PLL_SERIAL_2,
423 PLL_SERIAL_2_SRL_NOSC(div) |
424 PLL_SERIAL_2_SRL_PR(0));
425
426 /* set color matrix bypass flag: */
427 tda19988_register_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
428 MAT_CONTRL_MAT_SC(1));
429 tda19988_register_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
430
431 /* set BIAS tmds value: */
432 tda19988_register_write(priv, REG_ANA_GENERAL, 0x09);
433
434 /*
435 * Sync on rising HSYNC/VSYNC
436 */
437 reg = VIP_CNTRL_3_SYNC_HS;
438
439 /*
440 * TDA19988 requires high-active sync at input stage,
441 * so invert low-active sync provided by master encoder here
442 */
443 if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW)
444 reg |= VIP_CNTRL_3_H_TGL;
445 if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW)
446 reg |= VIP_CNTRL_3_V_TGL;
447 tda19988_register_write(priv, REG_VIP_CNTRL_3, reg);
448
449 tda19988_register_write(priv, REG_VIDFORMAT, 0x00);
450 tda19988_register_write16(priv, REG_REFPIX_MSB,
451 timing->hfront_porch.typ + 3);
452 tda19988_register_write16(priv, REG_REFLINE_MSB,
453 timing->vfront_porch.typ + 1);
454 tda19988_register_write16(priv, REG_NPIX_MSB, line_clocks);
455 tda19988_register_write16(priv, REG_NLINE_MSB, lines);
456 tda19988_register_write16(priv, REG_VS_LINE_STRT_1_MSB,
457 timing->vfront_porch.typ);
458 tda19988_register_write16(priv, REG_VS_PIX_STRT_1_MSB,
459 timing->hfront_porch.typ);
460 tda19988_register_write16(priv, REG_VS_LINE_END_1_MSB,
461 timing->vfront_porch.typ +
462 timing->vsync_len.typ);
463 tda19988_register_write16(priv, REG_VS_PIX_END_1_MSB,
464 timing->hfront_porch.typ);
465 tda19988_register_write16(priv, REG_VS_LINE_STRT_2_MSB, 0);
466 tda19988_register_write16(priv, REG_VS_PIX_STRT_2_MSB, 0);
467 tda19988_register_write16(priv, REG_VS_LINE_END_2_MSB, 0);
468 tda19988_register_write16(priv, REG_VS_PIX_END_2_MSB, 0);
469 tda19988_register_write16(priv, REG_HS_PIX_START_MSB,
470 timing->hfront_porch.typ);
471 tda19988_register_write16(priv, REG_HS_PIX_STOP_MSB,
472 timing->hfront_porch.typ +
473 timing->hsync_len.typ);
474 tda19988_register_write16(priv, REG_VWIN_START_1_MSB,
475 lines - timing->vactive.typ - 1);
476 tda19988_register_write16(priv, REG_VWIN_END_1_MSB, lines - 1);
477 tda19988_register_write16(priv, REG_VWIN_START_2_MSB, 0);
478 tda19988_register_write16(priv, REG_VWIN_END_2_MSB, 0);
479 tda19988_register_write16(priv, REG_DE_START_MSB,
480 line_clocks - timing->hactive.typ);
481 tda19988_register_write16(priv, REG_DE_STOP_MSB, line_clocks);
482
483 if (priv->revision == TDA19988) {
484 /* let incoming pixels fill the active space (if any) */
485 tda19988_register_write(priv, REG_ENABLE_SPACE, 0x00);
486 }
487
488 /*
489 * Always generate sync polarity relative to input sync and
490 * revert input stage toggled sync at output stage
491 */
492 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
493 if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW)
494 reg |= TBG_CNTRL_1_H_TGL;
495 if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW)
496 reg |= TBG_CNTRL_1_V_TGL;
497 tda19988_register_write(priv, REG_TBG_CNTRL_1, reg);
498
499 /* must be last register set: */
500 tda19988_register_write(priv, REG_TBG_CNTRL_0, 0);
501
502 /* turn on HDMI HDCP */
503 reg &= ~TBG_CNTRL_1_DWIN_DIS;
504 tda19988_register_write(priv, REG_TBG_CNTRL_1, reg);
505 tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
506 tda19988_register_set(priv, REG_TX33, TX33_HDMI);
507
508 mdelay(400);
509
510 /* enable video ports */
511 tda19988_register_write(priv, REG_ENA_VP_0, 0xff);
512 tda19988_register_write(priv, REG_ENA_VP_1, 0xff);
513 tda19988_register_write(priv, REG_ENA_VP_2, 0xff);
514 /* set muxing after enabling ports: */
515 tda19988_register_write(priv, REG_VIP_CNTRL_0,
516 VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3));
517 tda19988_register_write(priv, REG_VIP_CNTRL_1,
518 VIP_CNTRL_1_SWAP_C(4) | VIP_CNTRL_1_SWAP_D(5));
519 tda19988_register_write(priv, REG_VIP_CNTRL_2,
520 VIP_CNTRL_2_SWAP_E(0) | VIP_CNTRL_2_SWAP_F(1));
521
522 return 0;
523 }
524
525 struct dm_display_ops tda19988_ops = {
526 .read_edid = tda19988_read_edid,
527 .enable = tda19988_enable,
528 };
529
530 static const struct udevice_id tda19988_ids[] = {
531 { .compatible = "nxp,tda998x" },
532 { }
533 };
534
tda19988_probe(struct udevice * dev)535 static int tda19988_probe(struct udevice *dev)
536 {
537 u8 cec_addr, chip_addr, rev_lo, rev_hi;
538 int err;
539 struct tda19988_priv *priv = dev_get_priv(dev);
540
541 chip_addr = dev_read_addr(dev);
542 /* CEC I2C address is using TDA19988 I2C address configuration pins */
543 cec_addr = 0x34 + (chip_addr & 0x03);
544
545 err = i2c_get_chip_for_busnum(0, cec_addr, 1, &priv->cec_chip);
546 if (err) {
547 printf("cec i2c_get_chip_for_busnum returned %d\n", err);
548 return err;
549 }
550
551 err = i2c_get_chip_for_busnum(0, chip_addr, 1, &priv->chip);
552 if (err) {
553 printf("i2c_get_chip_for_busnum returned %d\n", err);
554 return err;
555 }
556
557 priv->current_page = 0xff;
558
559 /* wake up device */
560 dm_i2c_reg_write(priv->cec_chip, TDA19988_CEC_ENAMODS,
561 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
562
563 /* reset audio and I2C master */
564 tda19988_register_write(priv, REG_SOFTRESET,
565 SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
566 mdelay(50);
567 tda19988_register_write(priv, REG_SOFTRESET, 0);
568 mdelay(50);
569
570 /* reset transmitter */
571 tda19988_register_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
572 tda19988_register_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
573
574 /* PLL registers common configuration */
575 tda19988_register_write(priv, REG_PLL_SERIAL_1, 0x00);
576 tda19988_register_write(priv, REG_PLL_SERIAL_2,
577 PLL_SERIAL_2_SRL_NOSC(1));
578 tda19988_register_write(priv, REG_PLL_SERIAL_3, 0x00);
579 tda19988_register_write(priv, REG_SERIALIZER, 0x00);
580 tda19988_register_write(priv, REG_BUFFER_OUT, 0x00);
581 tda19988_register_write(priv, REG_PLL_SCG1, 0x00);
582 tda19988_register_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
583 tda19988_register_write(priv, REG_SEL_CLK,
584 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
585 tda19988_register_write(priv, REG_PLL_SCGN1, 0xfa);
586 tda19988_register_write(priv, REG_PLL_SCGN2, 0x00);
587 tda19988_register_write(priv, REG_PLL_SCGR1, 0x5b);
588 tda19988_register_write(priv, REG_PLL_SCGR2, 0x00);
589 tda19988_register_write(priv, REG_PLL_SCG2, 0x10);
590
591 /* Write the default value MUX register */
592 tda19988_register_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
593
594 /* read version */
595 rev_lo = dm_i2c_reg_read(priv->chip, REG_VERSION_LSB);
596 rev_hi = dm_i2c_reg_read(priv->chip, REG_VERSION_MSB);
597
598 /* mask off feature bits */
599 priv->revision = ((rev_hi << 8) | rev_lo) & ~0x30;
600
601 printf("HDMI: ");
602 switch (priv->revision) {
603 case TDA9989N2:
604 printf("TDA9989 n2\n");
605 break;
606 case TDA19989:
607 printf("TDA19989\n");
608 break;
609 case TDA19989N2:
610 printf("TDA19989 n2\n");
611 break;
612 case TDA19988:
613 printf("TDA19988\n");
614 break;
615 default:
616 printf("unknown TDA device: 0x%04x\n", priv->revision);
617 return -ENXIO;
618 }
619
620 /* after reset, enable DDC */
621 tda19988_register_write(priv, REG_DDC_DISABLE, 0x00);
622
623 /* set clock on DDC channel */
624 tda19988_register_write(priv, REG_TX3, 39);
625
626 /* if necessary, disable multi-master */
627 if (priv->revision == TDA19989)
628 tda19988_register_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
629
630 dm_i2c_reg_write(priv->cec_chip, REG_CEC_FRO_IM_CLK_CTRL,
631 CEC_FRO_IM_CLK_CTRL_GHOST_DIS |
632 CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
633 /* ensure interrupts are disabled */
634 dm_i2c_reg_write(priv->cec_chip, REG_CEC_RXSHPDINTENA, 0);
635 /* clear pending interrupts */
636 dm_i2c_reg_read(priv->cec_chip, REG_CEC_RXSHPDINT);
637 tda19988_register_read(priv, REG_INT_FLAGS_0);
638 tda19988_register_read(priv, REG_INT_FLAGS_1);
639 tda19988_register_read(priv, REG_INT_FLAGS_2);
640
641 /* enable EDID read irq */
642 tda19988_register_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
643
644 return 0;
645 }
646
647 U_BOOT_DRIVER(tda19988) = {
648 .name = "tda19988",
649 .id = UCLASS_DISPLAY,
650 .of_match = tda19988_ids,
651 .ops = &tda19988_ops,
652 .probe = tda19988_probe,
653 .priv_auto = sizeof(struct tda19988_priv),
654 };
655