Searched refs:INTER_REGS_BASE (Results 1 – 7 of 7) sorted by relevance
| /drivers/ddr/marvell/a38x/ |
| A D | ddr_ml_wrapper.h | 15 #define INTER_REGS_BASE SOC_REGS_PHY_BASE macro
126 writel(val, INTER_REGS_BASE + addr); in reg_write()
131 return readl(INTER_REGS_BASE + addr); in reg_read()
136 setbits_le32(INTER_REGS_BASE + addr, mask); in reg_bit_set()
141 clrbits_le32(INTER_REGS_BASE + addr, mask); in reg_bit_clr()
|
| A D | mv_ddr_plat.h | 19 #define INTER_REGS_BASE SOC_REGS_PHY_BASE macro
|
| /drivers/ddr/marvell/axp/ |
| A D | ddr3_init.h | 123 writel(val, INTER_REGS_BASE + addr); in reg_write()
128 return readl(INTER_REGS_BASE + addr); in reg_read()
133 setbits_le32(INTER_REGS_BASE + addr, mask); in reg_bit_set()
138 clrbits_le32(INTER_REGS_BASE + addr, mask); in reg_bit_clr()
|
| A D | ddr3_axp.h | 80 #define INTER_REGS_BASE SOC_REGS_PHY_BASE macro
|
| A D | ddr3_dfs.c | 59 writel(val, INTER_REGS_BASE + addr); in dfs_reg_write()
64 writel(val, INTER_REGS_BASE + addr); in dfs_reg_write()
|
| /drivers/ddr/marvell/a38x/old/ |
| A D | ddr3_init.h | 387 writel(val, INTER_REGS_BASE + addr); in reg_write()
392 return readl(INTER_REGS_BASE + addr); in reg_read()
397 setbits_le32(INTER_REGS_BASE + addr, mask); in reg_bit_set()
402 clrbits_le32(INTER_REGS_BASE + addr, mask); in reg_bit_clr()
|
| A D | ddr3_hws_hw_training_def.h | 50 #define INTER_REGS_BASE SOC_REGS_PHY_BASE macro
|
Completed in 20 milliseconds