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Searched refs:INTR_STATUS (Results 1 – 5 of 5) sorted by relevance

/drivers/mtd/nand/raw/
A Ddenali_spl.c47 intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank)); in wait_for_irq()
111 writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank)); in denali_send_pipeline_cmd()
A Ddenali.h205 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) macro
A Ddenali.c129 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); in denali_clear_irq()
146 irq_status = ioread32(denali->reg + INTR_STATUS(i)); in __denali_check_irq()
A Dcadence_nand.c221 writel_relaxed(irq_status->status, cadence->reg + INTR_STATUS); in cadence_nand_clear_interrupt()
232 irq_status->status = readl_relaxed(cadence->reg + INTR_STATUS); in cadence_nand_read_int_status()
688 writel_relaxed(0xFFFFFFFF, cadence->reg + INTR_STATUS); in cadence_nand_hw_init()
/drivers/i3c/master/
A Ddw-i3c-master.c235 status = readl(master->regs + INTR_STATUS); in dw_i3c_status_poll_timeout()
447 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_bus_init()
488 status = readl(master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
493 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
500 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
989 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_probe()

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