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Searched refs:MAX_CS_NUM (Results 1 – 17 of 17) sorted by relevance

/drivers/ddr/marvell/a38x/
A Dddr_topology_def.h77 enum mv_ddr_rtt_nom_park_evalue rtt_park[MAX_CS_NUM];
78 enum mv_ddr_rtt_wr_evalue rtt_wr[MAX_CS_NUM];
88 enum mv_ddr_ohm_evalue odt_p[MAX_CS_NUM];
89 enum mv_ddr_ohm_evalue odt_n[MAX_CS_NUM];
A Dxor.c18 static u32 ui_xor_regs_base_backup[MAX_CS_NUM + 1];
19 static u32 ui_xor_regs_mask_backup[MAX_CS_NUM + 1];
27 for (ui = 0; ui < MAX_CS_NUM + 1; ui++) in mv_sys_xor_init()
30 for (ui = 0; ui < MAX_CS_NUM + 1; ui++) in mv_sys_xor_init()
99 for (ui = 0; ui < MAX_CS_NUM + 1; ui++) in mv_sys_xor_finish()
102 for (ui = 0; ui < MAX_CS_NUM + 1; ui++) in mv_sys_xor_finish()
A Dmv_ddr_topology.c220 for (cs = 0; cs < MAX_CS_NUM; cs++) { in mv_ddr_cs_num_get()
323 if (cs_num > 0 && cs_num <= MAX_CS_NUM) in mv_ddr_rtt_park_get()
340 if (cs_num > 0 && cs_num <= MAX_CS_NUM) in mv_ddr_rtt_wr_get()
A Dddr3_training_leveling.c47 u8 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_read_leveling()
53 for (effective_cs = 0; effective_cs < MAX_CS_NUM; effective_cs++) in ddr3_tip_dynamic_read_leveling()
816 u8 wl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_write_leveling()
1725 enum rl_dqs_burst_state rl_state[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()
1737 u32 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()
1738 u32 rl_min_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()
1739 u32 rl_max_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()
1740 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst()
A Dmv_ddr_plat.c226 u32 dmin_phy_reg_table[MAX_BUS_NUM * MAX_CS_NUM][2] = {
1154 for (cs = 0; cs < MAX_CS_NUM; cs++) { in ddr3_fast_path_dynamic_cs_size_config()
1245 for (cs = 0; cs < MAX_CS_NUM; cs++) { in ddr3_restore_and_set_final_windows()
1292 for (cs = 0; cs < MAX_CS_NUM; cs++) { in ddr3_save_and_set_training_windows()
A Dmv_ddr_topology.h9 #define MAX_CS_NUM 4 macro
A Dddr3_debug.c116 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
117 u32 ctrl_adll1[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
118 u32 ctrl_level_phase[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
939 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
A Dddr3_training_pbs.c16 u8 result_mat_rx_dqs[MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];
23 u32 pbsdelay_per_pup[NUM_OF_PBS_MODES][MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];
A Dmv_ddr4_training.c274 for (cs = 0; cs < MAX_CS_NUM; cs++) { in mv_ddr4_phy_config()
A Dddr3_training_hw_algo.c47 u32 read_sample[MAX_CS_NUM]; in ddr3_tip_write_additional_odt_setting()
A Dddr3_training.c520 for (cs_cnt = 0; cs_cnt < MAX_CS_NUM; cs_cnt++) { in hws_ddr3_tip_init_controller()
2053 for (cs = 0; cs < MAX_CS_NUM; cs++) { in ddr3_tip_ddr3_reset_phy_regs()
3001 if (cs_num > 0 && cs_num <= MAX_CS_NUM) in mv_ddr_misl_phy_odt_p_get()
3016 if (cs_num > 0 && cs_num <= MAX_CS_NUM) in mv_ddr_misl_phy_odt_n_get()
/drivers/ddr/marvell/a38x/old/
A Dddr3_training_ip.h16 #define MAX_CS_NUM 4 macro
A Dddr3_training_static.c221 u32 rd_sample_dly[MAX_CS_NUM] = { 0 }; in ddr3_tip_read_leveling_static_config()
222 u32 rd_ready_del[MAX_CS_NUM] = { 0 }; in ddr3_tip_read_leveling_static_config()
A Dddr3_training_hw_algo.c53 u32 read_sample[MAX_CS_NUM]; in ddr3_tip_write_additional_odt_setting()
68 for (cs_num = 0; cs_num < MAX_CS_NUM; cs_num++) { in ddr3_tip_write_additional_odt_setting()
A Dddr3_training_pbs.c19 u8 result_mat_rx_dqs[MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];
A Dddr3_training.c277 for (cs = 0; cs < MAX_CS_NUM; cs++) { in calc_cs_num()
1913 for (cs = 0; cs < MAX_CS_NUM; cs++) { in ddr3_tip_ddr3_reset_phy_regs()
A Dddr3_debug.c749 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];

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