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Searched refs:MAX_DELAY (Results 1 – 5 of 5) sorted by relevance

/drivers/ddr/marvell/axp/
A Dddr3_read_leveling.c521 ui_max_delay = MAX_DELAY; in ddr3_read_leveling_single_cs_rl_mode()
943 ui_max_delay = MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1133 MAX_DELAY + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1135 MAX_DELAY + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1138 phase = tmp / MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1144 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1154 delay_s = dram_info->rl_val[cs][idx][PS] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1156 delay_e = dram_info->rl_val[cs][idx][PE] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1160 phase = tmp / MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1168 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
A Dddr3_hw_training.h123 #define MAX_DELAY 0x1F macro
A Dddr3_write_leveling.c1223 for (delay = 0; delay < MAX_DELAY; delay++) { in ddr3_write_leveling_single_cs()
1294 delay = MAX_DELAY; in ddr3_write_leveling_single_cs()
A Dddr3_pbs.c921 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail()
959 MAX_DELAY); in ddr3_rx_shift_dqs_to_first_fail()
A Dddr3_dqs.c916 && (centralization_high_limit[pup] == MAX_DELAY)) in ddr3_center_calc()

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