Searched refs:MUSB_CSR0_TXPKTRDY (Results 1 – 7 of 7) sorted by relevance
133 case MUSB_CSR0_TXPKTRDY: in wait_until_ep0_ready()134 if (!(csr & MUSB_CSR0_TXPKTRDY)) { in wait_until_ep0_ready()253 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); in ctrlreq_setup_phase()257 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); in ctrlreq_setup_phase()330 csr |= MUSB_CSR0_TXPKTRDY; in ctrlreq_out_data_phase()333 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); in ctrlreq_out_data_phase()353 csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT); in ctrlreq_out_status_phase()358 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); in ctrlreq_out_status_phase()
234 csr0 |= MUSB_CSR0_TXPKTRDY; in musb_ep0_tx_ready()243 csr0 |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_P_DATAEND); in musb_ep0_tx_ready_and_last()543 if (csr0 & MUSB_CSR0_TXPKTRDY) in musb_peri_ep0_tx()581 if (!(csr0 & MUSB_CSR0_TXPKTRDY)) in musb_peri_ep0_tx()
178 #define MUSB_CSR0_TXPKTRDY 0x0002 macro
529 u16 csr = MUSB_CSR0_TXPKTRDY; in ep0_txstate()616 musb->ackpend |= MUSB_CSR0_TXPKTRDY; in musb_read_setup()710 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) { in musb_g_ep0_irq()839 musb->ackpend = MUSB_CSR0_TXPKTRDY in musb_g_ep0_irq()
75 #define MUSB_CSR0_TXPKTRDY 0x0002 macro
123 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) in musb_h_ep0_flush_fifo()151 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; in musb_h_tx_start()1055 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; in musb_h_ep0_irq()1064 | MUSB_CSR0_TXPKTRDY; in musb_h_ep0_irq()
329 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); in musb_load_testpacket()
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