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Searched refs:MUX (Results 1 – 11 of 11) sorted by relevance

/drivers/clk/mediatek/
A Dclk-mt8516.c492 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
497 MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3),
513 MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
514 MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
517 MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
518 MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
521 MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2),
531 MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1),
532 MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2),
534 MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
[all …]
A Dclk-mt8183.c539 MUX(CLK_TOP_MUX_AXI, axi_parents, 0x40, 0, 2),
540 MUX(CLK_TOP_MUX_MM, mm_parents, 0x40, 8, 3),
541 MUX(CLK_TOP_MUX_IMG, img_parents, 0x40, 16, 3),
542 MUX(CLK_TOP_MUX_CAM, cam_parents, 0x40, 24, 4),
544 MUX(CLK_TOP_MUX_DSP, dsp_parents, 0x50, 0, 4),
549 MUX(CLK_TOP_MUX_MFG, mfg_parents, 0x60, 0, 2),
557 MUX(CLK_TOP_MUX_SPI, spi_parents, 0x70, 24, 2),
569 MUX(CLK_TOP_MUX_ATB, atb_parents, 0xa0, 0, 2),
577 MUX(CLK_TOP_MUX_SPM, spm_parents, 0xb0, 24, 1),
579 MUX(CLK_TOP_MUX_I2C, i2c_parents, 0xc0, 0, 2),
[all …]
A Dclk-mt8518.c1179 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
1190 MUX(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4),
1191 MUX(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3),
1194 MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
1195 MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
1196 MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
1197 MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3),
1204 MUX(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1),
1213 MUX(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4),
1225 MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3),
[all …]
A Dclk-mt7622.c378 MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1),
379 MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),
380 MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1),
381 MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),
382 MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1),
383 MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1),
A Dclk-mt7623.c754 MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3),
756 MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3),
757 MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3),
758 MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3),
A Dclk-mtk.h205 #define MUX(_id, _parents, _reg, _shift, _width) \ macro
/drivers/clk/exynos/
A Dclk-exynos850.c108 MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
112 MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
134 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
136 MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
140 MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
169 MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
198 MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
200 MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
202 MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
283 MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user",
[all …]
A Dclk.h100 #define MUX(_id, cname, pnames, o, s, w) \ macro
/drivers/i2c/muxes/
A DKconfig8 using a suitable I2C MUX driver.
17 using a suitable I2C MUX driver.
57 I2C busses connected through a MUX, which is controlled
/drivers/clk/
A Dclk_k210.c229 #define MUX(id, reg, shift, width) \ macro
234 MUX(K210_CLK_ACLK, K210_SYSCTL_SEL0, 0, 1) \
235 MUX(K210_CLK_SPI3, K210_SYSCTL_SEL0, 12, 1) \
236 MUX(K210_CLK_TIMER0, K210_SYSCTL_SEL0, 13, 1) \
237 MUX(K210_CLK_TIMER1, K210_SYSCTL_SEL0, 14, 1) \
238 MUX(K210_CLK_TIMER2, K210_SYSCTL_SEL0, 15, 1)
263 #undef MUX
/drivers/net/
A DKconfig36 bool "Enable Driver Model for MDIO MUX devices"
39 Enable driver model for MDIO MUX devices
75 bool "Sandbox: Mocked MDIO-MUX driver"
77 This driver implements dummy select/deselect ops mimicking a MUX on
1024 bool "MDIO MUX accessed as a register over I2C"
1063 bool "MDIO MUX accessed as a MMIO register access"
1070 bool "MDIO MUX for Amlogic Meson G12A SoCs"
1077 bool "MDIO MUX for Amlogic Meson GXL SoCs"

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