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Searched refs:MV_OK (Results 1 – 25 of 43) sorted by relevance

12

/drivers/ddr/marvell/a38x/
A Dmv_ddr4_mpr_pda_if.c179 return MV_OK; in mv_ddr4_mode_regs_init()
218 return MV_OK; in mv_ddr4_mpr_read_mode_enable()
247 return MV_OK; in mv_ddr4_mpr_mode_disable()
277 return MV_OK; in mv_ddr4_dq_decode()
322 return MV_OK; in mv_ddr4_mpr_read()
359 return MV_OK; in mv_ddr4_mpr_write_mode_enable()
372 return MV_OK; in mv_ddr4_mpr_write()
430 return MV_OK; in mv_ddr4_dq_pins_mapping()
471 return MV_OK; in mv_ddr4_vref_training_mode_ctrl()
519 return MV_OK; in mv_ddr4_vref_tap_set()
[all …]
A Dmv_ddr4_training.c53 if (status != MV_OK) in mv_ddr4_sdram_config()
59 if (status != MV_OK) in mv_ddr4_sdram_config()
68 if (status != MV_OK) in mv_ddr4_sdram_config()
74 if (status != MV_OK) in mv_ddr4_sdram_config()
80 if (status != MV_OK) in mv_ddr4_sdram_config()
86 if (status != MV_OK) in mv_ddr4_sdram_config()
95 if (status != MV_OK) in mv_ddr4_sdram_config()
101 return MV_OK; in mv_ddr4_sdram_config()
286 return MV_OK; in mv_ddr4_phy_config()
299 int status = MV_OK; in mv_ddr4_calibration_adjust()
[all …]
A Dmv_ddr4_training_leveling.c63 if (status != MV_OK) in mv_ddr4_xsb_comp_test()
90 if (status != MV_OK) in mv_ddr4_xsb_comp_test()
122 if (status != MV_OK) in mv_ddr4_xsb_comp_test()
128 if (status != MV_OK) in mv_ddr4_xsb_comp_test()
134 if (status != MV_OK) in mv_ddr4_xsb_comp_test()
145 if (status != MV_OK) in mv_ddr4_xsb_comp_test()
166 if (status != MV_OK) in mv_ddr4_xsb_comp_test()
171 if (status != MV_OK) in mv_ddr4_xsb_comp_test()
193 if (status != MV_OK) in mv_ddr4_xsb_comp_test()
249 int status = MV_OK; in mv_ddr4_dynamic_wl_supp()
[all …]
A Dmv_ddr_plat.c318 return MV_OK; in ddr3_tip_a38x_get_freq_config()
382 return MV_OK; in mv_ddr_is_odpg_done()
427 return MV_OK; in mv_ddr_is_training_done()
457 return MV_OK; in ddr3_tip_a38x_select_ddr_controller()
572 return MV_OK; in mv_ddr_sar_freq_get()
650 return MV_OK; in ddr3_tip_a38x_get_medium_freq()
659 return MV_OK; in ddr3_tip_a38x_get_device_info()
678 return MV_OK; in is_prfa_done()
701 return MV_OK; in prfa_write()
727 return MV_OK; in prfa_read()
[all …]
A Dddr3_init.c54 if (mv_ddr_early_init2() != MV_OK) in ddr3_init()
59 if (MV_OK != status) in ddr3_init()
71 if (status != MV_OK) { in ddr3_init()
79 if (MV_OK != status) { in ddr3_init()
86 if (MV_OK != status) { in ddr3_init()
101 return MV_OK; in ddr3_init()
166 if (MV_OK != status) { in mv_ddr_training_params_set()
171 return MV_OK; in mv_ddr_training_params_set()
A Dddr3_training_bist.c68 return MV_OK; in ddr3_tip_bist_activate()
112 return MV_OK; in ddr3_tip_bist_read_result()
160 return MV_OK; in hws_ddr3_run_bist()
176 return MV_OK; in ddr3_tip_bist_operation()
242 return MV_OK; in mv_ddr_tip_bist()
290 return MV_OK; in interval_init()
302 return MV_OK; in interval_set()
392 return MV_OK; in interval_proc()
420 return MV_OK; in mv_ddr_dm_to_dq_diff_get()
436 return MV_OK; in mv_ddr_bist_tx()
[all …]
A Dddr3_training.c246 return MV_OK; in ddr3_tip_pad_inv()
293 return MV_OK; in ddr3_tip_tune_training_params()
355 return MV_OK; in ddr3_tip_configure_cs()
701 return MV_OK; in hws_ddr3_tip_init_controller()
758 return MV_OK; in ddr3_tip_rev2_rank_control()
791 return MV_OK; in ddr3_tip_rev3_rank_control()
902 return MV_OK; in ddr3_pre_algo_config()
927 return MV_OK; in ddr3_post_algo_config()
974 int ret = MV_OK, ret_tune = MV_OK; in odt_test()
1026 return MV_OK; in ddr3_tip_if_write()
[all …]
A Dmv_ddr4_training_calibration.c327 return MV_OK; in mv_ddr4_dq_vref_calibration()
367 if (status != MV_OK) in mv_ddr4_centralization()
636 status = MV_OK; in mv_ddr4_centralization()
750 return MV_OK; in mv_ddr4_copt_get()
832 return MV_OK; in mv_ddr4_copt_get()
881 return MV_OK; in mv_ddr4_copt_get()
930 return MV_OK; in mv_ddr4_dqs_reposition()
1064 return MV_OK; in mv_ddr4_center_of_mass_calc()
1105 int status = MV_OK; in mv_ddr4_tap_tuning()
2010 return MV_OK; in mv_ddr4_receiver_calibration()
[all …]
A Dxor.c162 return MV_OK; in mv_xor_ctrl_set()
219 return MV_OK; in mv_xor_mem_init()
308 return MV_OK; in mv_xor_command_set()
314 return MV_OK; in mv_xor_command_set()
321 return MV_OK; in mv_xor_command_set()
327 return MV_OK; in mv_xor_command_set()
330 return MV_OK; in mv_xor_command_set()
463 return MV_OK; in mv_xor_transfer()
A Dddr3_training_leveling.c309 return MV_OK; in ddr3_tip_dynamic_read_leveling()
350 return MV_OK; in ddr3_tip_legacy_dynamic_write_leveling()
391 return MV_OK; in ddr3_tip_legacy_dynamic_read_leveling()
761 return MV_OK; in ddr3_tip_dynamic_per_bit_read_leveling()
799 return MV_OK; in ddr3_tip_calc_cs_mask()
1166 return MV_OK; in ddr3_tip_dynamic_write_leveling()
1279 return MV_OK; in ddr3_tip_dynamic_write_leveling_supp()
1519 return MV_OK; in ddr3_tip_dynamic_write_leveling_seq()
1557 return MV_OK; in ddr3_tip_dynamic_read_leveling_seq()
1596 return MV_OK; in ddr3_tip_dynamic_per_bit_read_leveling_seq()
[all …]
A Dddr3_training_ip_engine.c706 return MV_OK; in ddr3_tip_ip_training()
760 return MV_OK; in ddr3_tip_load_pattern_to_odpg()
784 return MV_OK; in ddr3_tip_configure_odpg()
827 return MV_OK; in ddr3_tip_process_result()
986 return MV_OK; in ddr3_tip_read_training_result()
1016 return MV_OK; in ddr3_tip_load_all_pattern_to_mem()
1097 return MV_OK; in ddr3_tip_load_pattern_to_mem()
1201 return MV_OK; in ddr3_tip_ip_training_wrapper_int()
1590 return MV_OK; in ddr3_tip_ip_training_wrapper()
1664 return MV_OK; in ddr3_tip_load_phy_values()
[all …]
/drivers/ddr/marvell/a38x/old/
A Dddr3_hws_hw_training.c63 return MV_OK; in ddr3_pre_algo_config()
72 if (MV_OK != status) { in ddr3_post_algo_config()
87 return MV_OK; in ddr3_post_algo_config()
97 if (MV_OK != status) { in ddr3_hws_hw_training()
116 if (MV_OK != status) { in ddr3_hws_hw_training()
122 if (MV_OK != status) { in ddr3_hws_hw_training()
128 if (MV_OK != status) { in ddr3_hws_hw_training()
135 if (MV_OK != status) { in ddr3_hws_hw_training()
141 if (MV_OK != status) { in ddr3_hws_hw_training()
146 return MV_OK; in ddr3_hws_hw_training()
A Dddr3_a38x.c246 return MV_OK; in ddr3_tip_a38x_get_freq_config()
275 return MV_OK; in ddr3_tip_a38x_pipe_enable()
300 return MV_OK; in ddr3_tip_a38x_if_write()
315 return MV_OK; in ddr3_tip_a38x_if_read()
339 return MV_OK; in ddr3_tip_a38x_select_ddr_controller()
445 return MV_OK; in ddr3_tip_init_a38x_silicon()
462 return MV_OK; in ddr3_a38x_update_topology_map()
475 return MV_OK; in ddr3_tip_init_a38x()
526 return MV_OK; in ddr3_tip_a38x_get_init_freq()
576 return MV_OK; in ddr3_tip_a38x_get_medium_freq()
[all …]
A Dddr3_training_bist.c133 return MV_OK; in ddr3_tip_bist_activate()
154 if (ret != MV_OK) in ddr3_tip_bist_read_result()
160 if (ret != MV_OK) in ddr3_tip_bist_read_result()
167 if (ret != MV_OK) in ddr3_tip_bist_read_result()
173 if (ret != MV_OK) in ddr3_tip_bist_read_result()
177 return MV_OK; in ddr3_tip_bist_read_result()
201 if (ret != MV_OK) { in hws_ddr3_run_bist()
212 if (ret != MV_OK) { in hws_ddr3_run_bist()
218 if (ret != MV_OK) { in hws_ddr3_run_bist()
225 return MV_OK; in hws_ddr3_run_bist()
[all …]
A Dddr3_training.c201 return MV_OK; in ddr3_tip_tune_training_params()
257 return MV_OK; in ddr3_tip_configure_cs()
294 return MV_OK; in calc_cs_num()
665 return MV_OK; in hws_ddr3_tip_init_controller()
717 return MV_OK; in hws_ddr3_tip_load_topology_map()
752 return MV_OK; in ddr3_tip_rank_control()
793 return MV_OK; in ddr3_tip_pad_inv()
801 int ret = MV_OK, ret_tune = MV_OK; in hws_ddr3_tip_run_alg()
846 int ret = MV_OK, ret_tune = MV_OK; in odt_test()
1023 return MV_OK; in ddr3_tip_bus_read()
[all …]
A Dddr3_training_leveling.c147 return MV_OK; in ddr3_tip_dynamic_read_leveling()
435 return MV_OK; in ddr3_tip_dynamic_read_leveling()
476 return MV_OK; in ddr3_tip_legacy_dynamic_write_leveling()
517 return MV_OK; in ddr3_tip_legacy_dynamic_read_leveling()
914 return MV_OK; in ddr3_tip_dynamic_per_bit_read_leveling()
951 return MV_OK; in ddr3_tip_calc_cs_mask()
1299 return MV_OK; in ddr3_tip_dynamic_write_leveling()
1419 return MV_OK; in ddr3_tip_dynamic_write_leveling_supp()
1597 return MV_OK; in ddr3_tip_wl_supp_one_clk_err_shift()
1655 return MV_OK; in ddr3_tip_wl_supp_align_err_shift()
[all …]
A Dddr3_a38x_training.c28 return MV_OK; in ddr3_silicon_init()
31 if (MV_OK != status) { in ddr3_silicon_init()
38 return MV_OK; in ddr3_silicon_init()
A Dddr3_init.c194 if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK) in ddr3_restore_and_set_final_windows()
278 return MV_OK; in ddr3_save_and_set_training_windows()
334 return MV_OK; in ddr3_init()
384 if (MV_OK != status) in ddr3_init()
393 if (MV_OK != status) { in ddr3_init()
419 return MV_OK; in ddr3_init()
596 if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK) in ddr3_fast_path_dynamic_cs_size_config()
657 return MV_OK; in ddr3_fast_path_dynamic_cs_size_config()
740 return MV_OK; in ddr3_calc_mem_cs_size()
763 if (MV_OK != status) { in ddr3_hws_tune_training_params()
[all …]
A Dddr3_training_static.c70 return MV_OK; in ddr3_tip_init_specific_reg_config()
85 return MV_OK; in ddr3_tip_init_static_config_db()
141 return MV_OK; in ddr3_tip_static_round_trip_arr_build()
199 return MV_OK; in ddr3_tip_write_leveling_static_config()
336 return MV_OK; in ddr3_tip_read_leveling_static_config()
359 if (ret != MV_OK) { in ddr3_tip_run_static_alg()
393 return MV_OK; in ddr3_tip_run_static_alg()
422 return MV_OK; in ddr3_tip_static_init_controller()
462 return MV_OK; in ddr3_tip_static_phy_init_controller()
536 return MV_OK; in ddr3_tip_configure_phy()
A Dddr3_debug.c151 return MV_OK; in ddr3_tip_reg_dump()
166 return MV_OK; in ddr3_tip_init_config_func()
294 return MV_OK; in print_device_info()
364 return MV_OK; in ddr3_tip_print_log()
495 return MV_OK; in ddr3_tip_print_log()
656 return MV_OK; in ddr3_tip_print_stability_log()
665 return MV_OK; in ddr3_tip_register_xsb_info()
806 return MV_OK; in ddr3_tip_print_adll()
1175 return MV_OK;
1197 return MV_OK; in print_adll()
[all …]
/drivers/ddr/marvell/axp/
A Dddr3_hw_training.c205 if (MV_OK != in ddr3_hw_training()
230 if (MV_OK != in ddr3_hw_training()
238 if (MV_OK != in ddr3_hw_training()
482 return MV_OK; in ddr3_hw_training()
682 return MV_OK; in ddr3_load_patterns()
860 return MV_OK; in ddr3_read_training_results()
971 return MV_OK; in ddr3_training_suspend_resume()
1043 return MV_OK; in ddr3_get_min_max_read_sample_delay()
1065 return MV_OK; in ddr3_get_min_max_rl_phase()
1083 return MV_OK; in ddr3_odt_activate()
[all …]
A Dxor.c151 return MV_OK; in mv_xor_ctrl_set()
205 return MV_OK; in mv_xor_mem_init()
316 return MV_OK; in mv_xor_transfer()
406 return MV_OK; in mv_xor_cmd_set()
412 return MV_OK; in mv_xor_cmd_set()
418 return MV_OK; in mv_xor_cmd_set()
424 return MV_OK; in mv_xor_cmd_set()
428 return MV_OK; in mv_xor_cmd_set()
A Dddr3_dqs.c202 return MV_OK; in ddr3_dqs_centralization_rx()
282 return MV_OK; in ddr3_dqs_centralization_tx()
814 return MV_OK; in ddr3_find_adll_limits()
838 return MV_OK; in ddr3_check_window_limits()
875 return MV_OK; in ddr3_check_window_limits()
924 if (MV_OK != in ddr3_center_calc()
933 if (MV_OK != in ddr3_center_calc()
1101 return MV_OK; in ddr3_special_pattern_i_search()
1250 return MV_OK; in ddr3_special_pattern_ii_search()
1321 return MV_OK; in ddr3_set_dqs_centralization_results()
[all …]
A Dddr3_pbs.c392 return MV_OK; in ddr3_pbs_tx()
509 return MV_OK; in ddr3_tx_shift_dqs_adll_step_before_fail()
904 return MV_OK; in ddr3_pbs_rx()
1079 return MV_OK; in ddr3_rx_shift_dqs_to_first_fail()
1239 if (MV_OK != in ddr3_pbs_per_bit()
1364 return MV_OK; in ddr3_pbs_per_bit()
1406 return MV_OK; in ddr3_pbs_per_bit()
1504 return MV_OK; in ddr3_set_pbs_results()
1570 if (MV_OK != in ddr3_load_pbs_patterns()
1580 if (MV_OK != in ddr3_load_pbs_patterns()
[all …]
A Dddr3_sdram.c199 return MV_OK; in ddr3_sdram_compare()
263 return MV_OK; in ddr3_sdram_dm_compare()
421 return MV_OK; in ddr3_sdram_pbs_compare()
480 return MV_OK; in ddr3_sdram_direct_compare()
535 if (mv_xor_transfer(chan, MV_DMA, channel.desc_phys_addr) != MV_OK) in ddr3_dram_sram_burst()
546 return MV_OK; in ddr3_dram_sram_burst()
595 return MV_OK; in ddr3_dram_sram_read()
632 return MV_OK; in ddr3_sdram_dqs_compare()

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