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Searched refs:ODPG_DATA_CTRL_REG (Results 1 – 7 of 7) sorted by relevance

/drivers/ddr/marvell/a38x/
A Dddr3_training_bist.c34 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in ddr3_tip_bist_activate()
39 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in ddr3_tip_bist_activate()
66 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_bist_activate()
434 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in mv_ddr_bist_tx()
452 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in mv_ddr_odpg_bist_prepare()
457 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in mv_ddr_odpg_bist_prepare()
511 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in mv_ddr_dm_vw_get()
534 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, in mv_ddr_dm_vw_get()
539 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, in mv_ddr_dm_vw_get()
571 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, in mv_ddr_dm_vw_get()
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A Dmv_ddr4_training_leveling.c60 status = ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG, in mv_ddr4_xsb_comp_test()
87 status = ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG, in mv_ddr4_xsb_comp_test()
142 status = ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG, in mv_ddr4_xsb_comp_test()
163 status = ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG, in mv_ddr4_xsb_comp_test()
A Dddr3_training_ip_engine.c521 ODPG_DATA_CTRL_REG, in ddr3_tip_ip_training()
530 ODPG_DATA_CTRL_REG, 0x3 | cs_num << 26, in ddr3_tip_ip_training()
700 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_ip_training()
780 ODPG_DATA_CTRL_REG, data_value, 0xaffffffc); in ddr3_tip_configure_odpg()
863 ODPG_DATA_CTRL_REG, (cs_num_type << 26), (3 << 26))); in ddr3_tip_read_training_result()
1041 ODPG_DATA_CTRL_REG, reg_data, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_mem()
1045 ODPG_DATA_CTRL_REG, (0x1 | (effective_cs << 26)), in ddr3_tip_load_pattern_to_mem()
1070 ODPG_DATA_CTRL_REG, (u32)(0x1 << 31), in ddr3_tip_load_pattern_to_mem()
1081 ODPG_DATA_CTRL_REG, (0x1 << 30), (u32) (0x3 << 30))); in ddr3_tip_load_pattern_to_mem()
1086 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_mem()
A Dddr3_training_leveling.c89 ODPG_DATA_CTRL_REG, 0x3, 0x3)); in ddr3_tip_dynamic_read_leveling()
196 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_dynamic_read_leveling()
253 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
262 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
463 ODPG_DATA_CTRL_REG, 0x3, 0x3)); in ddr3_tip_dynamic_per_bit_read_leveling()
568 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_dynamic_per_bit_read_leveling()
732 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
740 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
1840 ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG, in mv_ddr_rl_dqs_burst()
A Dmv_ddr_regs.h279 #define ODPG_DATA_CTRL_REG 0x1630 macro
A Dmv_ddr4_mpr_pda_if.c587 status = ddr3_tip_if_write(dev_num, access_type, if_id, ODPG_DATA_CTRL_REG, val, mask); in mv_ddr4_pda_pattern_odpg_load()
A Dmv_ddr4_training_calibration.c2320 ddr3_tip_if_read(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, data_read, MASK_ALL_BITS); in refresh()
2323 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, (0 << 26), (3 << 26)); in refresh()
2329 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, (1 << 26), (3 << 26)); in refresh()
2335 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, data_read[0] , MASK_ALL_BITS); in refresh()

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