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Searched refs:P (Results 1 – 9 of 9) sorted by relevance

/drivers/ddr/marvell/axp/
A Dddr3_write_leveling.c122 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
149 [P], 1); in ddr3_write_leveling_hw()
347 [pup_num][P] + in ddr3_wl_supplement()
352 [P] = phase; in ddr3_wl_supplement()
368 [P]; in ddr3_wl_supplement()
385 [P] = phase; in ddr3_wl_supplement()
545 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw_reg_dimm()
555 dram_info->wl_val[cs][pup][P] = in ddr3_write_leveling_hw_reg_dimm()
585 [P], 1); in ddr3_write_leveling_hw_reg_dimm()
1269 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_single_cs()
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A Dddr3_read_leveling.c111 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
140 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
271 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw()
290 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
1128 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1143 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1167 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
A Dddr3_hw_training.h113 #define P 2 macro
/drivers/gpio/
A Drzg2l-gpio.c18 setbits_8(data->base + P(port), BIT(pin)); in rzg2l_gpio_set()
20 clrbits_8(data->base + P(port), BIT(pin)); in rzg2l_gpio_set()
37 return !!(readb(data->base + P(port)) & BIT(pin)); in rzg2l_gpio_get_value()
A Dgpio-rza1.c14 #define P(bank) (0x0000 + (bank) * 4) macro
/drivers/pinctrl/rockchip/
A Dpinctrl-rockchip.h464 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ argument
465 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
/drivers/pinctrl/renesas/
A Dpinctrl-rza1.c16 #define P(bank) (0x0000 + (bank) * 4) macro
A Drzg2l-pfc.c361 port_offset = P(port); in rzg2l_pinconf_set()
/drivers/pci/
A DKconfig188 PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.

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