Searched refs:PBS_TX_PHY_REG (Results 1 – 6 of 6) sorted by relevance
| /drivers/ddr/marvell/a38x/ |
| A D | mv_ddr4_training_calibration.c | 1153 reg_addr = PBS_TX_PHY_REG(effective_cs, DQSP_PAD); in mv_ddr4_tap_tuning()
1159 reg_addr = PBS_TX_PHY_REG(effective_cs, DQSN_PAD); in mv_ddr4_tap_tuning()
1614 reg_addr = PBS_TX_PHY_REG(effective_cs, DQSP_PAD); in mv_ddr4_tap_tuning()
2158 PBS_TX_PHY_REG(cs, dm_pad), &dm_pbs); in mv_ddr4_dm_tuning()
2168 PBS_TX_PHY_REG(cs, dm_pad), dm_pbs); in mv_ddr4_dm_tuning()
2177 PBS_TX_PHY_REG(cs, pad), ®_val); in mv_ddr4_dm_tuning()
2202 PBS_TX_PHY_REG(cs, pad), in mv_ddr4_dm_tuning()
2254 PBS_TX_PHY_REG(cs, pad), in mv_ddr4_dm_tuning()
2278 PBS_TX_PHY_REG(cs, pad), in mv_ddr4_dm_tuning()
2284 PBS_TX_PHY_REG(cs, dm_pad), &dm_pbs); in mv_ddr4_dm_tuning()
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| A D | ddr3_training_pbs.c | 777 PBS_TX_PHY_REG(effective_cs, 0); in ddr3_tip_pbs()
945 PBS_TX_PHY_REG(cs_num , 0); in ddr3_tip_print_pbs_result()
995 PBS_TX_PHY_REG(effective_cs, 0); in ddr3_tip_clean_pbs_result()
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| A D | mv_ddr_regs.h | 508 #define PBS_TX_PHY_REG(cs, bit) (PBS_TX_PHY_BASE + (cs) * 0x10 + (bit)) macro
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| A D | ddr3_training.c | 2036 PBS_TX_PHY_REG(effective_cs, DQSP_PAD), 0)); in ddr3_tip_ddr3_reset_phy_regs()
2044 PBS_TX_PHY_REG(effective_cs, DQSN_PAD), 0)); in ddr3_tip_ddr3_reset_phy_regs()
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| /drivers/ddr/marvell/a38x/old/ |
| A D | ddr3_training_pbs.c | 781 (PBS_TX_PHY_REG + effective_cs * 0x10); in ddr3_tip_pbs()
940 (PBS_TX_PHY_REG + cs_num * 0x10); in ddr3_tip_print_pbs_result()
978 (PBS_TX_PHY_REG + effective_cs * 0x10); in ddr3_tip_clean_pbs_result()
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| A D | ddr3_training_ip_flow.h | 217 #define PBS_TX_PHY_REG 0x10 macro
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