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Searched refs:PCIE_LINK_WIDTH_SPEED_CONTROL (Results 1 – 3 of 3) sorted by relevance

/drivers/pci/
A Dpci-rcar-gen4.c133 clrbits_le32(rcar->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, in rcar_gen4_pcie_speed_change()
136 setbits_le32(rcar->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, in rcar_gen4_pcie_speed_change()
140 val = readl(rcar->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); in rcar_gen4_pcie_speed_change()
A Dpcie_dw_common.c46 lwsc = readl(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); in dw_pcie_link_set_max_link_width()
67 writel(lwsc, pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); in dw_pcie_link_set_max_link_width()
400 setbits_le32(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, in pcie_dw_setup_host()
A Dpcie_dw_common.h88 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C macro

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