Searched refs:REG2G (Results 1 – 3 of 3) sorted by relevance
| /drivers/ram/starfive/ |
| A D | ddrcsr_boot.c | 78 {0x4, 0x0, 0x10010006, (F_SET | REG2G)},
81 {0x4, 0x0, 0x10020000, (F_SET | REG2G)},
84 {0x4, 0x0, 0x10030031, (F_SET | REG2G)},
87 {0x4, 0x0, 0x100b0033, (F_SET | REG2G)},
90 {0x4, 0x0, 0x10160016, (F_SET | REG2G)},
157 {0x4, 0x0, 0x10010036, (F_SET | REG2G)},
160 {0x4, 0x0, 0x10010036, (F_SET | REG2G)},
163 {0x4, 0x0, 0x10030031, (F_SET | REG2G)},
167 {0x4, 0x0, 0x100b0066, (F_SET | REG2G)},
170 {0x4, 0x0, 0x10160016, (F_SET | REG2G)},
[all …]
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| A D | ddrphy_start.c | 81 {11, 0xfffffff0, 0x00000005, (F_CLRSET | REG2G)},
94 {289, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
95 {313, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
96 {337, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
97 {361, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
164 {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG4G | REG2G | F_SET)},
188 {1062, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
189 {1318, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
190 {1574, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
259 mask = REG2G; in ddr_phy_start()
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| A D | starfive_ddr.h | 29 #define REG2G BIT(30) macro
35 #define REGALL (REG2G | REG4G | REG8G)
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