Searched refs:REG8G (Results 1 – 3 of 3) sorted by relevance
| /drivers/ram/starfive/ |
| A D | ddrcsr_boot.c | 77 {0x4, 0x0, 0x30010006, (F_SET | REG4G | REG8G)},
80 {0x4, 0x0, 0x30020000, (F_SET | REG4G | REG8G)},
83 {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)},
86 {0x4, 0x0, 0x300b0033, (F_SET | REG4G | REG8G)},
89 {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)},
156 {0x4, 0x0, 0x30010036, (F_SET | REG4G | REG8G)},
159 {0x4, 0x0, 0x3002001b, (F_SET | REG4G | REG8G)},
162 {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)},
166 {0x4, 0x0, 0x300b0036, (F_SET | REG8G)},
169 {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)},
[all …]
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| A D | ddrphy_start.c | 90 {289, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
91 {313, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
92 {337, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
93 {361, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
165 {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG8G | F_SET)},
191 {1062, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
192 {1318, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
193 {1574, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
267 mask = REG8G; in ddr_phy_start()
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| A D | starfive_ddr.h | 31 #define REG8G BIT(28) macro
35 #define REGALL (REG2G | REG4G | REG8G)
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