Searched refs:RL (Results 1 – 3 of 3) sorted by relevance
| /drivers/ddr/microchip/ |
| A D | ddr2.c | 37 writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) | in ddr2_phy_init()
167 ((RL - WL + 3) << 28)), &ctrl->dlycfg0); in ddr2_ctrl_init()
176 (((RL + 5) >> 4) << 29) | in ddr2_ctrl_init()
185 ((RL + 3) << 28)), &ctrl->dlycfg2); in ddr2_ctrl_init()
195 writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3), in ddr2_ctrl_init()
227 host_load_cmd(ctrl, 5, temp, LOAD_MODE_CMD | (RL << 28) | (2 << 24), in ddr2_ctrl_init()
240 host_load_cmd(ctrl, 9, temp, LOAD_MODE_CMD | (RL << 28) | (3 << 24), in ddr2_ctrl_init()
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| A D | ddr2_timing.h | 17 #define RL 5 macro
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| /drivers/ram/renesas/dbsc5/ |
| A D | dram.c | 1421 u32 RL; member
2182 priv->RL = js1[priv->js1_ind].RLset1; in dbsc5_ddrtbl_calc()
2225 { PI_CASLAT_F2, priv->RL }, in dbsc5_ddrtbl_load()
2583 dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(0), priv->RL); in dbsc5_dbsc_regset()
2622 priv->RL + 4 + priv->js2[JS2_tWCK2DQO_HF] - in dbsc5_dbsc_regset()
2649 tmp[2] = (priv->RL * 4) + in dbsc5_dbsc_regset()
2654 tmp[3] = (priv->RL * 4) + 4 - in dbsc5_dbsc_regset()
2689 tmp[2] = priv->RL * 4; in dbsc5_dbsc_regset()
2733 tmp[1] = ((priv->RL + 4) * 4) + 3; in dbsc5_dbsc_regset()
2745 tmp[0] = priv->RL + 4 + 0 + 1; in dbsc5_dbsc_regset()
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