Searched refs:RL_PHY_REG (Results 1 – 12 of 12) sorted by relevance
| /drivers/ddr/marvell/a38x/old/ |
| A D | ddr3_training_ip_flow.h | 214 #define RL_PHY_REG 0x2 macro
238 #define PHY_READ_DELAY(cs) RL_PHY_REG
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| A D | ddr3_training_leveling.c | 407 RL_PHY_REG + in ddr3_tip_dynamic_read_leveling()
842 RL_PHY_REG + in ddr3_tip_dynamic_per_bit_read_leveling()
890 ddr3_tip_write_cs_result(dev_num, RL_PHY_REG); in ddr3_tip_dynamic_per_bit_read_leveling()
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| A D | ddr3_training_hw_algo.c | 85 RL_PHY_REG + CS_REG_VALUE(cs_num), in ddr3_tip_write_additional_odt_setting()
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| A D | ddr3_training_ip_engine.c | 1200 RL_PHY_REG + in ddr3_tip_load_phy_values()
1228 RL_PHY_REG + in ddr3_tip_load_phy_values()
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| A D | ddr3_debug.c | 589 RL_PHY_REG + csindex * 4, in ddr3_tip_print_stability_log()
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| A D | ddr3_training.c | 1897 RL_PHY_REG + CS_REG_VALUE(effective_cs), in ddr3_tip_ddr3_reset_phy_regs()
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| /drivers/ddr/marvell/a38x/ |
| A D | ddr3_training_leveling.c | 282 RL_PHY_REG(effective_cs), in ddr3_tip_dynamic_read_leveling()
690 RL_PHY_REG(effective_cs), in ddr3_tip_dynamic_per_bit_read_leveling()
737 ddr3_tip_write_cs_result(dev_num, RL_PHY_REG(0)); in ddr3_tip_dynamic_per_bit_read_leveling()
1869 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
2048 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
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| A D | mv_ddr_regs.h | 463 #define RL_PHY_REG(cs) (RL_PHY_BASE + (cs) * 0x4) macro
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| A D | ddr3_training_hw_algo.c | 80 RL_PHY_REG(cs_num), in ddr3_tip_write_additional_odt_setting()
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| A D | ddr3_debug.c | 718 RL_PHY_REG(csindex), in ddr3_tip_print_stability_log()
1246 reg = (direction == 0) ? WL_PHY_REG(cs) : RL_PHY_REG(cs); in ddr3_tip_run_leveling_sweep_test()
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| A D | ddr3_training_ip_engine.c | 1628 RL_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
1650 RL_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
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| A D | ddr3_training.c | 2015 RL_PHY_REG(effective_cs), in ddr3_tip_ddr3_reset_phy_regs()
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