Searched refs:S (Results 1 – 8 of 8) sorted by relevance
| /drivers/usb/tcpm/ |
| A D | tcpm-internal.h | 11 S(INVALID_STATE), \
12 S(TOGGLING), \
13 S(SRC_UNATTACHED), \
15 S(SRC_ATTACHED), \
16 S(SRC_STARTUP), \
21 S(SRC_READY), \
27 S(SNK_ATTACHED), \
28 S(SNK_STARTUP), \
36 S(SNK_READY), \
46 S(SOFT_RESET), \
[all …]
|
| /drivers/block/ |
| A D | rkmtd.c | 957 u8 S[256], K[256], temp; in rkmtd_rc4() local
963 S[i] = (u8)i; in rkmtd_rc4()
972 temp = S[i]; in rkmtd_rc4()
973 S[i] = S[j]; in rkmtd_rc4()
974 S[j] = temp; in rkmtd_rc4()
981 j = (j + S[i]) % 256; in rkmtd_rc4()
982 temp = S[i]; in rkmtd_rc4()
983 S[i] = S[j]; in rkmtd_rc4()
984 S[j] = temp; in rkmtd_rc4()
985 t = (S[i] + (S[j] % 256)) % 256; in rkmtd_rc4()
[all …]
|
| /drivers/ddr/marvell/axp/ |
| A D | ddr3_read_leveling.c | 117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
347 if (info->rl_val[cs][idx][S] == RL_UNLOCK_STATE) { in overrun()
362 info->rl_val[cs][idx][S] = RL_FINAL_STATE; in overrun()
422 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_rl_mode()
578 if (dram_info->rl_val[cs][idx][S] in ddr3_read_leveling_single_cs_rl_mode()
607 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
776 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_window_mode()
833 if (dram_info->rl_val[cs][idx][S] == RL_WINDOW_STATE) { in ddr3_read_leveling_single_cs_window_mode()
849 dram_info->rl_val[cs][idx][S]++; in ddr3_read_leveling_single_cs_window_mode()
856 } else if (dram_info->rl_val[cs][idx][S] == in ddr3_read_leveling_single_cs_window_mode()
[all …]
|
| A D | ddr3_write_leveling.c | 124 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw()
341 [S] = 1; in ddr3_wl_supplement()
410 sum += dram_info->wl_val[cs][pup][S]; in ddr3_wl_supplement()
413 sum += dram_info->wl_val[cs][ECC_PUP][S]; in ddr3_wl_supplement()
560 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw_reg_dimm()
1267 if (dram_info->wl_val[cs][pup][S] == 0) { in ddr3_write_leveling_single_cs()
1279 && (dram_info->wl_val[cs][pup][S] == 0)) { in ddr3_write_leveling_single_cs()
1285 dram_info->wl_val[cs][pup][S] = 1; in ddr3_write_leveling_single_cs()
|
| A D | ddr3_hw_training.h | 111 #define S 0 macro
|
| /drivers/video/fonts/ |
| A D | .gitignore | 1 *.S
|
| /drivers/net/bnxt/ |
| A D | bnxt.h | 97 #define NEXT_IDX(N, S) (((N) + 1) & ((S) - 1)) argument
|
| /drivers/timer/ |
| A D | Kconfig | 244 Select this to enable support for a generic RISC-V S-Mode timer
|
Completed in 21 milliseconds