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Searched refs:SDRAM_OP_REG (Results 1 – 5 of 5) sorted by relevance

/drivers/ddr/marvell/a38x/
A Dmv_ddr4_mpr_pda_if.c208 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, SDRAM_OP_REG, in mv_ddr4_mpr_read_mode_enable()
213 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f, SDRAM_OP_REG, in mv_ddr4_mpr_read_mode_enable()
237 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, SDRAM_OP_REG, in mv_ddr4_mpr_mode_disable()
242 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f, SDRAM_OP_REG, in mv_ddr4_mpr_mode_disable()
349 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, SDRAM_OP_REG, in mv_ddr4_mpr_write_mode_enable()
354 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f, SDRAM_OP_REG, in mv_ddr4_mpr_write_mode_enable()
462 status = ddr3_tip_if_write(dev_num, access_type, if_id, SDRAM_OP_REG, val, mask); in mv_ddr4_vref_training_mode_ctrl()
466 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f, SDRAM_OP_REG, in mv_ddr4_vref_training_mode_ctrl()
559 status = ddr3_tip_if_write(dev_num, access_type, if_id, SDRAM_OP_REG, val, mask); in mv_ddr4_vref_set()
658 status = ddr3_tip_if_write(dev_num, access_type, if_id, SDRAM_OP_REG, val, mask); in mv_ddr4_pda_ctrl()
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A Dddr3_training_leveling.c861 if_id, SDRAM_OP_REG, in ddr3_tip_dynamic_write_leveling()
870 SDRAM_OP_REG, MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_dynamic_write_leveling()
1706 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, SDRAM_OP_REG, in mpr_rd_frmt_config()
1713 CMD_NORMAL, SDRAM_OP_CMD_MASK, SDRAM_OP_REG, in mpr_rd_frmt_config()
1809 SDRAM_OP_REG, reg_val, reg_mask); in mv_ddr_rl_dqs_burst()
1811 CMD_NORMAL, SDRAM_OP_CMD_MASK, SDRAM_OP_REG, in mv_ddr_rl_dqs_burst()
1829 SDRAM_OP_REG, reg_val, reg_mask); in mv_ddr_rl_dqs_burst()
1831 CMD_NORMAL, SDRAM_OP_CMD_MASK, SDRAM_OP_REG, in mv_ddr_rl_dqs_burst()
2069 SDRAM_OP_REG, reg_val, reg_mask); in mv_ddr_rl_dqs_burst()
2071 CMD_NORMAL, SDRAM_OP_CMD_MASK, SDRAM_OP_REG, in mv_ddr_rl_dqs_burst()
A Dmv_ddr_regs.h131 #define SDRAM_OP_REG 0x1418 macro
A Dddr3_training.c1554 SDRAM_OP_REG, 0x2, 0xf1f)); in ddr3_tip_freq_set()
1557 SDRAM_OP_REG, MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_freq_set()
1936 SDRAM_OP_REG, in ddr3_tip_write_mrs_cmd()
1943 0x1f, SDRAM_OP_REG, in ddr3_tip_write_mrs_cmd()
A Dmv_ddr4_training_calibration.c2324 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, SDRAM_OP_REG, 0xe02, 0xf1f); in refresh()
2325 …if (ddr3_tip_if_polling(0, ACCESS_TYPE_UNICAST, 0, 0, 0x1f, SDRAM_OP_REG, MAX_POLLING_ITERATIONS) … in refresh()
2330 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, SDRAM_OP_REG, 0xd02, 0xf1f); in refresh()
2331 …if (ddr3_tip_if_polling(0, ACCESS_TYPE_UNICAST, 0, 0, 0x1f, SDRAM_OP_REG, MAX_POLLING_ITERATIONS) … in refresh()

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