1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Texas Instruments ICSSG Ethernet driver 3 * 4 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 */ 7 8 #ifndef __NET_TI_ICSSG_SWITCH_MAP_H 9 #define __NET_TI_ICSSG_SWITCH_MAP_H 10 11 /*Time after which FDB entries are checked for aged out values. Value in nanoseconds*/ 12 #define FDB_AGEING_TIMEOUT_OFFSET 0x0014 13 14 /*default VLAN tag for Host Port*/ 15 #define HOST_PORT_DF_VLAN_OFFSET 0x001C 16 17 /*Same as HOST_PORT_DF_VLAN_OFFSET*/ 18 #define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET 19 20 /*default VLAN tag for P1 Port*/ 21 #define P1_PORT_DF_VLAN_OFFSET 0x0020 22 23 /*Same as P1_PORT_DF_VLAN_OFFSET*/ 24 #define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET 25 26 /*default VLAN tag for P2 Port*/ 27 #define P2_PORT_DF_VLAN_OFFSET 0x0024 28 29 /*Same as P2_PORT_DF_VLAN_OFFSET*/ 30 #define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET 31 32 /*VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000*/ 33 #define VLAN_STATIC_REG_TABLE_OFFSET 0x0100 34 35 /*VLAN-FID Table offset for EMAC*/ 36 #define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET 37 38 /*packet descriptor Q reserved memory*/ 39 #define PORT_DESC0_HI 0x2104 40 41 /*packet descriptor Q reserved memory*/ 42 #define PORT_DESC0_LO 0x2F6C 43 44 /*packet descriptor Q reserved memory*/ 45 #define PORT_DESC1_HI 0x3DD4 46 47 /*packet descriptor Q reserved memory*/ 48 #define PORT_DESC1_LO 0x4C3C 49 50 /*packet descriptor Q reserved memory*/ 51 #define HOST_DESC0_HI 0x5AA4 52 53 /*packet descriptor Q reserved memory*/ 54 #define HOST_DESC0_LO 0x5F0C 55 56 /*packet descriptor Q reserved memory*/ 57 #define HOST_DESC1_HI 0x6374 58 59 /*packet descriptor Q reserved memory*/ 60 #define HOST_DESC1_LO 0x67DC 61 62 /*special packet descriptor Q reserved memory*/ 63 #define HOST_SPPD0 0x7AAC 64 65 /*special packet descriptor Q reserved memory*/ 66 #define HOST_SPPD1 0x7EAC 67 68 /*_Small_Description_*/ 69 #define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET 0x83EC 70 71 /*IEP count hi roll over count*/ 72 #define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET 0x83F4 73 74 /*_Small_Description_*/ 75 #define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET 0x83F8 76 77 /*Set clock descriptor*/ 78 #define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET 0x83FC 79 80 /*_Small_Description_*/ 81 #define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET 0x843C 82 83 /*_Small_Description_*/ 84 #define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_COUNT_OFFSET 0x8440 85 86 /*_Small_Description_*/ 87 #define TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET 0x8444 88 89 /*Control variable to generate SYNC1*/ 90 #define TIMESYNC_FW_WC_ISOM_PIN_SIGNAL_EN_OFFSET 0x844C 91 92 /*SystemTime Sync0 periodicity*/ 93 #define TIMESYNC_FW_ST_SYNCOUT_PERIOD_OFFSET 0x8450 94 95 /*pktTxDelay for P1 = link speed dependent p1 mac delay + p1 phy delay*/ 96 #define TIMESYNC_FW_WC_PKTTXDELAY_P1_OFFSET 0x8454 97 98 /*pktTxDelay for P2 = link speed dependent p2 mac delay + p2 phy delay*/ 99 #define TIMESYNC_FW_WC_PKTTXDELAY_P2_OFFSET 0x8458 100 101 /*Set clock operation done signal for next task*/ 102 #define TIMESYNC_FW_SIG_PNFW_OFFSET 0x845C 103 104 /*Set clock operation done signal for next task*/ 105 #define TIMESYNC_FW_SIG_TIMESYNCFW_OFFSET 0x8460 106 107 /*New list is copied at this time*/ 108 #define TAS_CONFIG_CHANGE_TIME 0x000C 109 110 /*config change error counter*/ 111 #define TAS_CONFIG_CHANGE_ERROR_COUNTER 0x0014 112 113 /*TAS List update pending flag*/ 114 #define TAS_CONFIG_PENDING 0x0018 115 116 /*TAS list update trigger flag*/ 117 #define TAS_CONFIG_CHANGE 0x0019 118 119 /*List length for new TAS schedule*/ 120 #define TAS_ADMIN_LIST_LENGTH 0x001A 121 122 /*Currently active TAS list index*/ 123 #define TAS_ACTIVE_LIST_INDEX 0x001B 124 125 /*Cycle time for the new TAS schedule*/ 126 #define TAS_ADMIN_CYCLE_TIME 0x001C 127 128 /*Cycle counts remaining till the TAS list update*/ 129 #define TAS_CONFIG_CHANGE_CYCLE_COUNT 0x0020 130 131 /*Base Flow ID for sending packets to Host for Slice0*/ 132 #define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 0x0024 133 134 /*Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET*/ 135 #define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 136 137 /*Base Flow ID for sending mgmt and Tx TS to Host for Slice0*/ 138 #define PSI_L_MGMT_FLOW_ID_OFFSET 0x0026 139 140 /*Same as PSI_L_MGMT_FLOW_ID_OFFSET*/ 141 #define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET PSI_L_MGMT_FLOW_ID_OFFSET 142 143 /*Queue number for Special packets written here*/ 144 #define SPL_PKT_DEFAULT_PRIORITY 0x0028 145 146 /*Express Preemptible Queue Mask*/ 147 #define EXPRESS_PRE_EMPTIVE_Q_MASK 0x0029 148 149 /*Port1/Port2 Default Queue number for untagged packets, only 1B is used*/ 150 #define QUEUE_NUM_UNTAGGED 0x002A 151 152 /*Stores the table used for priority regeneration. 1B per PCP/Queue*/ 153 #define PORT_Q_PRIORITY_REGEN_OFFSET 0x002C 154 155 /* For marking Packet as priority/express (this feature is disabled) or 156 * cut-through/S&F. 157 */ 158 #define EXPRESS_PRE_EMPTIVE_Q_MAP 0x0034 159 160 /*Stores the table used for priority mapping. 1B per PCP/Queue*/ 161 #define PORT_Q_PRIORITY_MAPPING_OFFSET 0x003C 162 163 /*TAS gate mask for windows list0*/ 164 #define TAS_GATE_MASK_LIST0 0x0100 165 166 /*TAS gate mask for windows list1*/ 167 #define TAS_GATE_MASK_LIST1 0x0350 168 169 /*Memory to Enable/Disable Preemption on TX side*/ 170 #define PRE_EMPTION_ENABLE_TX 0x05A0 171 172 /*Active State of Preemption on TX side*/ 173 #define PRE_EMPTION_ACTIVE_TX 0x05A1 174 175 /*Memory to Enable/Disable Verify State Machine Preemption*/ 176 #define PRE_EMPTION_ENABLE_VERIFY 0x05A2 177 178 /*Verify Status of State Machine*/ 179 #define PRE_EMPTION_VERIFY_STATUS 0x05A3 180 181 /*Non Final Fragment Size supported by Link Partner*/ 182 #define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE 0x05A4 183 184 /*Non Final Fragment Size supported by Firmware*/ 185 #define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL 0x05A6 186 187 /*Time in ms the State machine waits for respond packet*/ 188 #define PRE_EMPTION_VERIFY_TIME 0x05A8 189 190 /*Memory used for R30 related management commands*/ 191 #define MGR_R30_CMD_OFFSET 0x05AC 192 193 /*HW Buffer Pool0 base address*/ 194 #define BUFFER_POOL_0_ADDR_OFFSET 0x05BC 195 196 /*16B for Host Egress MSMC Q (Pre-emptible) context*/ 197 #define HOST_RX_Q_PRE_CONTEXT_OFFSET 0x0684 198 199 /*Buffer for 8 FDB entries to be added by 'Add Multiple FDB entries IOCTL*/ 200 #define FDB_CMD_BUFFER 0x0894 201 202 /*16B for Host Egress MSMC Q (Express) context*/ 203 #define HOST_RX_Q_EXP_CONTEXT_OFFSET 0x0940 204 205 /*Start of 32 bits PA_STAT counters*/ 206 #define PA_STAT_32b_START_OFFSET 0x0080 207 208 #endif 209 /* __NET_TI_ICSSG_SWITCH_MAP_H */ 210