Searched refs:TRAINING_REG (Results 1 – 5 of 5) sorted by relevance
| /drivers/ddr/marvell/a38x/old/ |
| A D | ddr3_training_leveling.c | 85 PARAM_NOT_CARE, TRAINING_REG, in ddr3_tip_dynamic_read_leveling()
94 PARAM_NOT_CARE, TRAINING_REG, in ddr3_tip_dynamic_read_leveling()
102 (u32)(1 << 31), TRAINING_REG, in ddr3_tip_dynamic_read_leveling()
119 TRAINING_REG, data_read, 1 << 30)); in ddr3_tip_dynamic_read_leveling()
132 TRAINING_REG, 0, 0xf1ffff)); in ddr3_tip_dynamic_read_leveling()
268 TRAINING_REG, (1 << 24) | (1 << 20), in ddr3_tip_dynamic_read_leveling()
272 TRAINING_REG, (u32)(1 << 31), (u32)(1 << 31))); in ddr3_tip_dynamic_read_leveling()
463 TRAINING_REG, (0x80000008 | cs_mask), in ddr3_tip_legacy_dynamic_write_leveling()
468 (u32)0x80000000, TRAINING_REG, in ddr3_tip_legacy_dynamic_write_leveling()
509 (u32)0x80000000, TRAINING_REG, in ddr3_tip_legacy_dynamic_read_leveling()
[all …]
|
| A D | ddr3_training_ip_flow.h | 128 #define TRAINING_REG 0x15b0 macro
|
| /drivers/ddr/marvell/a38x/ |
| A D | mv_ddr4_training_leveling.c | 133 TRAINING_REG, 0x80000000, 0x80000000); in mv_ddr4_xsb_comp_test()
302 TRAINING_REG, 0x0, 0x80000000); in mv_ddr4_dynamic_pb_wl_supp()
425 TRAINING_REG, 0x0, 0x80000000); in mv_ddr4_dynamic_pb_wl_supp()
|
| A D | ddr3_training_leveling.c | 169 TRAINING_REG, (1 << 24) | (1 << 20), in ddr3_tip_dynamic_read_leveling()
173 TRAINING_REG, (u32)(1 << 31), (u32)(1 << 31))); in ddr3_tip_dynamic_read_leveling()
337 TRAINING_REG, (0x80000008 | cs_mask), in ddr3_tip_legacy_dynamic_write_leveling()
342 (u32)0x80000000, TRAINING_REG, in ddr3_tip_legacy_dynamic_write_leveling()
375 (dev_num, ACCESS_TYPE_MULTICAST, 0, TRAINING_REG, in ddr3_tip_legacy_dynamic_read_leveling()
383 (u32)0x80000000, TRAINING_REG, in ddr3_tip_legacy_dynamic_read_leveling()
541 TRAINING_REG, (1 << 24) | (1 << 20), in ddr3_tip_dynamic_per_bit_read_leveling()
545 TRAINING_REG, (u32)(1 << 31), (u32)(1 << 31))); in ddr3_tip_dynamic_per_bit_read_leveling()
1770 ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, TRAINING_REG, in mv_ddr_rl_dqs_burst()
1775 ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, TRAINING_REG, in mv_ddr_rl_dqs_burst()
|
| A D | mv_ddr_regs.h | 239 #define TRAINING_REG 0x15b0 macro
|
Completed in 18 milliseconds